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Aurabindo Pillaialexdeucher
Aurabindo Pillai
authored and
alexdeucher
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drm/amd/display: Add some missing register headers for DCN401
Add some HDCP related register headers for future use. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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‎drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h‎

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@@ -9776,6 +9776,14 @@
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#define regDIG0_DIG_BE_CNTL_BASE_IDX 2
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#define regDIG0_DIG_BE_EN_CNTL 0x20bd
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#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
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#define regDIG0_HDCP_INT_CONTROL 0x20c0
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#define regDIG0_HDCP_INT_CONTROL_BASE_IDX 2
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#define regDIG0_HDCP_LINK0_STATUS 0x20c1
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#define regDIG0_HDCP_LINK0_STATUS_BASE_IDX 2
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#define regDIG0_HDCP_I2C_CONTROL_0 0x20c2
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#define regDIG0_HDCP_I2C_CONTROL_0_BASE_IDX 2
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#define regDIG0_HDCP_I2C_CONTROL_1 0x20c3
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#define regDIG0_HDCP_I2C_CONTROL_1_BASE_IDX 2
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#define regDIG0_TMDS_CNTL 0x20e4
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#define regDIG0_TMDS_CNTL_BASE_IDX 2
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#define regDIG0_TMDS_CONTROL_CHAR 0x20e5
@@ -10081,6 +10089,12 @@
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#define regDIG1_DIG_BE_CNTL_BASE_IDX 2
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#define regDIG1_DIG_BE_EN_CNTL 0x21e1
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#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
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#define regDIG1_HDCP_INT_CONTROL 0x21e4
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#define regDIG1_HDCP_INT_CONTROL_BASE_IDX 2
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#define regDIG1_HDCP_I2C_CONTROL_0 0x21e6
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#define regDIG1_HDCP_I2C_CONTROL_0_BASE_IDX 2
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#define regDIG1_HDCP_I2C_CONTROL_1 0x21e7
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#define regDIG1_HDCP_I2C_CONTROL_1_BASE_IDX 2
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#define regDIG1_TMDS_CNTL 0x2208
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#define regDIG1_TMDS_CNTL_BASE_IDX 2
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#define regDIG1_TMDS_CONTROL_CHAR 0x2209
@@ -10386,6 +10400,12 @@
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#define regDIG2_DIG_BE_CNTL_BASE_IDX 2
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#define regDIG2_DIG_BE_EN_CNTL 0x2305
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#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
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#define regDIG2_HDCP_INT_CONTROL 0x2308
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#define regDIG2_HDCP_INT_CONTROL_BASE_IDX 2
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#define regDIG2_HDCP_I2C_CONTROL_0 0x230a
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#define regDIG2_HDCP_I2C_CONTROL_0_BASE_IDX 2
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#define regDIG2_HDCP_I2C_CONTROL_1 0x230b
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#define regDIG2_HDCP_I2C_CONTROL_1_BASE_IDX 2
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#define regDIG2_TMDS_CNTL 0x232c
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#define regDIG2_TMDS_CNTL_BASE_IDX 2
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#define regDIG2_TMDS_CONTROL_CHAR 0x232d
@@ -10691,6 +10711,12 @@
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#define regDIG3_DIG_BE_CNTL_BASE_IDX 2
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#define regDIG3_DIG_BE_EN_CNTL 0x2429
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#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
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#define regDIG3_HDCP_INT_CONTROL 0x242c
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#define regDIG3_HDCP_INT_CONTROL_BASE_IDX 2
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#define regDIG3_HDCP_I2C_CONTROL_0 0x242e
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#define regDIG3_HDCP_I2C_CONTROL_0_BASE_IDX 2
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#define regDIG3_HDCP_I2C_CONTROL_1 0x242f
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#define regDIG3_HDCP_I2C_CONTROL_1_BASE_IDX 2
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#define regDIG3_TMDS_CNTL 0x2450
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#define regDIG3_TMDS_CNTL_BASE_IDX 2
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#define regDIG3_TMDS_CONTROL_CHAR 0x2451

‎drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h‎

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@@ -2847,6 +2847,14 @@
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_AUTH_FAIL_INTERRUPT_DEST__SHIFT 0x1
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT 0x2
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT 0x3
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT 0x4
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_FAIL_INTERRUPT_DEST__SHIFT 0x5
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT 0x6
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT 0x7
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT 0x8
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_FAIL_INTERRUPT_DEST__SHIFT 0x9
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT 0xa
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT 0xb
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT 0xc
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_FAIL_INTERRUPT_DEST__SHIFT 0xd
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT 0xe
@@ -2871,6 +2879,14 @@
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_AUTH_FAIL_INTERRUPT_DEST_MASK 0x00000002L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST_MASK 0x00000004L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_DONE_INTERRUPT_DEST_MASK 0x00000008L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_SUCCESS_INTERRUPT_DEST_MASK 0x00000010L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_FAIL_INTERRUPT_DEST_MASK 0x00000020L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST_MASK 0x00000040L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_DONE_INTERRUPT_DEST_MASK 0x00000080L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_SUCCESS_INTERRUPT_DEST_MASK 0x00000100L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_FAIL_INTERRUPT_DEST_MASK 0x00000200L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST_MASK 0x00000400L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_DONE_INTERRUPT_DEST_MASK 0x00000800L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_SUCCESS_INTERRUPT_DEST_MASK 0x00001000L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_FAIL_INTERRUPT_DEST_MASK 0x00002000L
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#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST_MASK 0x00004000L

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