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Merge branch 'am65-cpsw-rx-dscp-prio-map'
Roger Quadros says: ==================== net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX Configure default DSCP to User Priority mapping registers as per: https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 and https://datatracker.ietf.org/doc/html/rfc8622#section-11 Also update Priority to Thread maping to be compliant with IEEE802.1Q-2014. Priority Code Point (PCP) 2 is higher priority than PCP 0 (Best Effort). PCP 1 (Background) is lower priority than PCP 0 (Best Effort). --- Changes in v4: - Updated default DSCP to User Priority mapping as per https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 and https://datatracker.ietf.org/doc/html/rfc8622#section-11 - Link to v3: https://lore.kernel.org/r/20241109-am65-cpsw-multi-rx-dscp-v3-0-1cfb76928490@kernel.org Changes in v3: - Added Reviewed-by tag to patch 1 - Added macros for DSCP PRI field size and DSCP PRI per register - Drop unnecessary readl() in am65_cpsw_port_set_dscp_map() - Link to v2: https://lore.kernel.org/r/20241107-am65-cpsw-multi-rx-dscp-v2-0-9e9cd1920035@kernel.org Changes in v2: - Updated references to more recent standard IEEE802.1Q-2014. - Dropped reference to web link which might change in the future. - Typo fix in commit log. - Link to v1: https://lore.kernel.org/r/20241105-am65-cpsw-multi-rx-dscp-v1-0-38db85333c88@kernel.org ==================== Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2 parents ac60031 + a208f41 commit d7ef9ee

2 files changed

Lines changed: 122 additions & 14 deletions

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‎drivers/net/ethernet/ti/am65-cpsw-nuss.c‎

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,8 @@
7171
#define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020
7272
#define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024
7373

74+
#define AM65_CPSW_PORTN_REG_CTL 0x004
75+
#define AM65_CPSW_PORTN_REG_DSCP_MAP 0x120
7476
#define AM65_CPSW_PORTN_REG_SA_L 0x308
7577
#define AM65_CPSW_PORTN_REG_SA_H 0x30c
7678
#define AM65_CPSW_PORTN_REG_TS_CTL 0x310
@@ -94,6 +96,10 @@
9496
/* AM65_CPSW_PORT_REG_PRI_CTL */
9597
#define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8)
9698

99+
/* AM65_CPSW_PN_REG_CTL */
100+
#define AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN BIT(1)
101+
#define AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN BIT(2)
102+
97103
/* AM65_CPSW_PN_TS_CTL register fields */
98104
#define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4)
99105
#define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5)
@@ -176,6 +182,99 @@ static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave,
176182
writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L);
177183
}
178184

185+
#define AM65_CPSW_DSCP_MAX GENMASK(5, 0)
186+
#define AM65_CPSW_PRI_MAX GENMASK(2, 0)
187+
#define AM65_CPSW_DSCP_PRI_PER_REG 8
188+
#define AM65_CPSW_DSCP_PRI_SIZE 4 /* in bits */
189+
static int am65_cpsw_port_set_dscp_map(struct am65_cpsw_port *slave, u8 dscp, u8 pri)
190+
{
191+
int reg_ofs;
192+
int bit_ofs;
193+
u32 val;
194+
195+
if (dscp > AM65_CPSW_DSCP_MAX)
196+
return -EINVAL;
197+
198+
if (pri > AM65_CPSW_PRI_MAX)
199+
return -EINVAL;
200+
201+
/* 32-bit register offset to this dscp */
202+
reg_ofs = (dscp / AM65_CPSW_DSCP_PRI_PER_REG) * 4;
203+
/* bit field offset to this dscp */
204+
bit_ofs = AM65_CPSW_DSCP_PRI_SIZE * (dscp % AM65_CPSW_DSCP_PRI_PER_REG);
205+
206+
val = readl(slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs);
207+
val &= ~(AM65_CPSW_PRI_MAX << bit_ofs); /* clear */
208+
val |= pri << bit_ofs; /* set */
209+
writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs);
210+
211+
return 0;
212+
}
213+
214+
static void am65_cpsw_port_enable_dscp_map(struct am65_cpsw_port *slave)
215+
{
216+
int dscp, pri;
217+
u32 val;
218+
219+
/* Default DSCP to User Priority mapping as per:
220+
* https://datatracker.ietf.org/doc/html/rfc8325#section-4.3
221+
* and
222+
* https://datatracker.ietf.org/doc/html/rfc8622#section-11
223+
*/
224+
for (dscp = 0; dscp <= AM65_CPSW_DSCP_MAX; dscp++) {
225+
switch (dscp) {
226+
case 56: /* CS7 */
227+
case 48: /* CS6 */
228+
pri = 7;
229+
break;
230+
case 46: /* EF */
231+
case 44: /* VA */
232+
pri = 6;
233+
break;
234+
case 40: /* CS5 */
235+
pri = 5;
236+
break;
237+
case 34: /* AF41 */
238+
case 36: /* AF42 */
239+
case 38: /* AF43 */
240+
case 32: /* CS4 */
241+
case 26: /* AF31 */
242+
case 28: /* AF32 */
243+
case 30: /* AF33 */
244+
case 24: /* CS3 */
245+
pri = 4;
246+
break;
247+
case 18: /* AF21 */
248+
case 20: /* AF22 */
249+
case 22: /* AF23 */
250+
pri = 3;
251+
break;
252+
case 16: /* CS2 */
253+
case 10: /* AF11 */
254+
case 12: /* AF12 */
255+
case 14: /* AF13 */
256+
case 0: /* DF */
257+
pri = 0;
258+
break;
259+
case 8: /* CS1 */
260+
case 1: /* LE */
261+
pri = 1;
262+
break;
263+
default:
264+
pri = 0;
265+
break;
266+
}
267+
268+
am65_cpsw_port_set_dscp_map(slave, dscp, pri);
269+
}
270+
271+
/* enable port IPV4 and IPV6 DSCP for this port */
272+
val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL);
273+
val |= AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN |
274+
AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN;
275+
writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL);
276+
}
277+
179278
static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port)
180279
{
181280
cpsw_sl_reset(port->slave.mac_sl, 100);
@@ -916,6 +1015,7 @@ static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev)
9161015
common->usage_count++;
9171016

9181017
am65_cpsw_port_set_sl_mac(port, ndev->dev_addr);
1018+
am65_cpsw_port_enable_dscp_map(port);
9191019

9201020
if (common->is_emac_mode)
9211021
am65_cpsw_init_port_emac_ale(port);

‎drivers/net/ethernet/ti/cpsw_ale.c‎

Lines changed: 22 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1704,26 +1704,34 @@ static void cpsw_ale_policer_reset(struct cpsw_ale *ale)
17041704
void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
17051705
{
17061706
int pri, idx;
1707-
/* IEEE802.1D-2004, Standard for Local and metropolitan area networks
1708-
* Table G-2 - Traffic type acronyms
1709-
* Table G-3 - Defining traffic types
1710-
* User priority values 1 and 2 effectively communicate a lower
1711-
* priority than 0. In the below table 0 is assigned to higher priority
1712-
* thread than 1 and 2 wherever possible.
1713-
* The below table maps which thread the user priority needs to be
1707+
1708+
/* Reference:
1709+
* IEEE802.1Q-2014, Standard for Local and metropolitan area networks
1710+
* Table I-2 - Traffic type acronyms
1711+
* Table I-3 - Defining traffic types
1712+
* Section I.4 Traffic types and priority values, states:
1713+
* "0 is thus used both for default priority and for Best Effort, and
1714+
* Background is associated with a priority value of 1. This means
1715+
* that the value 1 effectively communicates a lower priority than 0."
1716+
*
1717+
* In the table below, Priority Code Point (PCP) 0 is assigned
1718+
* to a higher priority thread than PCP 1 wherever possible.
1719+
* The table maps which thread the PCP traffic needs to be
17141720
* sent to for a given number of threads (RX channels). Upper threads
17151721
* have higher priority.
17161722
* e.g. if number of threads is 8 then user priority 0 will map to
1717-
* pri_thread_map[8-1][0] i.e. thread 2
1723+
* pri_thread_map[8-1][0] i.e. thread 1
17181724
*/
1719-
int pri_thread_map[8][8] = { { 0, 0, 0, 0, 0, 0, 0, 0, },
1725+
1726+
int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */
1727+
{ 0, 0, 0, 0, 0, 0, 0, 0, },
17201728
{ 0, 0, 0, 0, 1, 1, 1, 1, },
17211729
{ 0, 0, 0, 0, 1, 1, 2, 2, },
1722-
{ 1, 0, 0, 1, 2, 2, 3, 3, },
1723-
{ 1, 0, 0, 1, 2, 3, 4, 4, },
1724-
{ 1, 0, 0, 2, 3, 4, 5, 5, },
1725-
{ 1, 0, 0, 2, 3, 4, 5, 6, },
1726-
{ 2, 0, 1, 3, 4, 5, 6, 7, } };
1730+
{ 0, 0, 1, 1, 2, 2, 3, 3, },
1731+
{ 0, 0, 1, 1, 2, 2, 3, 4, },
1732+
{ 1, 0, 2, 2, 3, 3, 4, 5, },
1733+
{ 1, 0, 2, 3, 4, 4, 5, 6, },
1734+
{ 1, 0, 2, 3, 4, 5, 6, 7 } };
17271735

17281736
cpsw_ale_policer_reset(ale);
17291737

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