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tiwaitiwai
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Merge tag 'asoc-fix-v6.5-merge-window' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Fixes that got left after v6.4 These were some changes in my v6.4 branch that never got sent as fixes, none of them super urgent thankfully.
2 parents 8d2a0cd + d900d9a commit d81c203

4 files changed

Lines changed: 102 additions & 72 deletions

File tree

‎sound/soc/codecs/cs43130.h‎

Lines changed: 69 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -381,88 +381,88 @@ struct cs43130_clk_gen {
381381

382382
/* frm_size = 16 */
383383
static const struct cs43130_clk_gen cs43130_16_clk_gen[] = {
384-
{ 22579200, 32000, .v = { 441, 10, }, },
385-
{ 22579200, 44100, .v = { 32, 1, }, },
386-
{ 22579200, 48000, .v = { 147, 5, }, },
387-
{ 22579200, 88200, .v = { 16, 1, }, },
388-
{ 22579200, 96000, .v = { 147, 10, }, },
389-
{ 22579200, 176400, .v = { 8, 1, }, },
390-
{ 22579200, 192000, .v = { 147, 20, }, },
391-
{ 22579200, 352800, .v = { 4, 1, }, },
392-
{ 22579200, 384000, .v = { 147, 40, }, },
393-
{ 24576000, 32000, .v = { 48, 1, }, },
394-
{ 24576000, 44100, .v = { 5120, 147, }, },
395-
{ 24576000, 48000, .v = { 32, 1, }, },
396-
{ 24576000, 88200, .v = { 2560, 147, }, },
397-
{ 24576000, 96000, .v = { 16, 1, }, },
398-
{ 24576000, 176400, .v = { 1280, 147, }, },
399-
{ 24576000, 192000, .v = { 8, 1, }, },
400-
{ 24576000, 352800, .v = { 640, 147, }, },
401-
{ 24576000, 384000, .v = { 4, 1, }, },
384+
{ 22579200, 32000, .v = { 10, 441, }, },
385+
{ 22579200, 44100, .v = { 1, 32, }, },
386+
{ 22579200, 48000, .v = { 5, 147, }, },
387+
{ 22579200, 88200, .v = { 1, 16, }, },
388+
{ 22579200, 96000, .v = { 10, 147, }, },
389+
{ 22579200, 176400, .v = { 1, 8, }, },
390+
{ 22579200, 192000, .v = { 20, 147, }, },
391+
{ 22579200, 352800, .v = { 1, 4, }, },
392+
{ 22579200, 384000, .v = { 40, 147, }, },
393+
{ 24576000, 32000, .v = { 1, 48, }, },
394+
{ 24576000, 44100, .v = { 147, 5120, }, },
395+
{ 24576000, 48000, .v = { 1, 32, }, },
396+
{ 24576000, 88200, .v = { 147, 2560, }, },
397+
{ 24576000, 96000, .v = { 1, 16, }, },
398+
{ 24576000, 176400, .v = { 147, 1280, }, },
399+
{ 24576000, 192000, .v = { 1, 8, }, },
400+
{ 24576000, 352800, .v = { 147, 640, }, },
401+
{ 24576000, 384000, .v = { 1, 4, }, },
402402
};
403403

404404
/* frm_size = 32 */
405405
static const struct cs43130_clk_gen cs43130_32_clk_gen[] = {
406-
{ 22579200, 32000, .v = { 441, 20, }, },
407-
{ 22579200, 44100, .v = { 16, 1, }, },
408-
{ 22579200, 48000, .v = { 147, 10, }, },
409-
{ 22579200, 88200, .v = { 8, 1, }, },
410-
{ 22579200, 96000, .v = { 147, 20, }, },
411-
{ 22579200, 176400, .v = { 4, 1, }, },
412-
{ 22579200, 192000, .v = { 147, 40, }, },
413-
{ 22579200, 352800, .v = { 2, 1, }, },
414-
{ 22579200, 384000, .v = { 147, 80, }, },
415-
{ 24576000, 32000, .v = { 24, 1, }, },
416-
{ 24576000, 44100, .v = { 2560, 147, }, },
417-
{ 24576000, 48000, .v = { 16, 1, }, },
418-
{ 24576000, 88200, .v = { 1280, 147, }, },
419-
{ 24576000, 96000, .v = { 8, 1, }, },
420-
{ 24576000, 176400, .v = { 640, 147, }, },
421-
{ 24576000, 192000, .v = { 4, 1, }, },
422-
{ 24576000, 352800, .v = { 320, 147, }, },
423-
{ 24576000, 384000, .v = { 2, 1, }, },
406+
{ 22579200, 32000, .v = { 20, 441, }, },
407+
{ 22579200, 44100, .v = { 1, 16, }, },
408+
{ 22579200, 48000, .v = { 10, 147, }, },
409+
{ 22579200, 88200, .v = { 1, 8, }, },
410+
{ 22579200, 96000, .v = { 20, 147, }, },
411+
{ 22579200, 176400, .v = { 1, 4, }, },
412+
{ 22579200, 192000, .v = { 40, 147, }, },
413+
{ 22579200, 352800, .v = { 1, 2, }, },
414+
{ 22579200, 384000, .v = { 80, 147, }, },
415+
{ 24576000, 32000, .v = { 1, 24, }, },
416+
{ 24576000, 44100, .v = { 147, 2560, }, },
417+
{ 24576000, 48000, .v = { 1, 16, }, },
418+
{ 24576000, 88200, .v = { 147, 1280, }, },
419+
{ 24576000, 96000, .v = { 1, 8, }, },
420+
{ 24576000, 176400, .v = { 147, 640, }, },
421+
{ 24576000, 192000, .v = { 1, 4, }, },
422+
{ 24576000, 352800, .v = { 147, 320, }, },
423+
{ 24576000, 384000, .v = { 1, 2, }, },
424424
};
425425

426426
/* frm_size = 48 */
427427
static const struct cs43130_clk_gen cs43130_48_clk_gen[] = {
428-
{ 22579200, 32000, .v = { 147, 100, }, },
429-
{ 22579200, 44100, .v = { 32, 3, }, },
430-
{ 22579200, 48000, .v = { 49, 5, }, },
431-
{ 22579200, 88200, .v = { 16, 3, }, },
432-
{ 22579200, 96000, .v = { 49, 10, }, },
433-
{ 22579200, 176400, .v = { 8, 3, }, },
434-
{ 22579200, 192000, .v = { 49, 20, }, },
435-
{ 22579200, 352800, .v = { 4, 3, }, },
436-
{ 22579200, 384000, .v = { 49, 40, }, },
437-
{ 24576000, 32000, .v = { 16, 1, }, },
438-
{ 24576000, 44100, .v = { 5120, 441, }, },
439-
{ 24576000, 48000, .v = { 32, 3, }, },
440-
{ 24576000, 88200, .v = { 2560, 441, }, },
441-
{ 24576000, 96000, .v = { 16, 3, }, },
442-
{ 24576000, 176400, .v = { 1280, 441, }, },
443-
{ 24576000, 192000, .v = { 8, 3, }, },
444-
{ 24576000, 352800, .v = { 640, 441, }, },
445-
{ 24576000, 384000, .v = { 4, 3, }, },
428+
{ 22579200, 32000, .v = { 100, 147, }, },
429+
{ 22579200, 44100, .v = { 3, 32, }, },
430+
{ 22579200, 48000, .v = { 5, 49, }, },
431+
{ 22579200, 88200, .v = { 3, 16, }, },
432+
{ 22579200, 96000, .v = { 10, 49, }, },
433+
{ 22579200, 176400, .v = { 3, 8, }, },
434+
{ 22579200, 192000, .v = { 20, 49, }, },
435+
{ 22579200, 352800, .v = { 3, 4, }, },
436+
{ 22579200, 384000, .v = { 40, 49, }, },
437+
{ 24576000, 32000, .v = { 1, 16, }, },
438+
{ 24576000, 44100, .v = { 441, 5120, }, },
439+
{ 24576000, 48000, .v = { 3, 32, }, },
440+
{ 24576000, 88200, .v = { 441, 2560, }, },
441+
{ 24576000, 96000, .v = { 3, 16, }, },
442+
{ 24576000, 176400, .v = { 441, 1280, }, },
443+
{ 24576000, 192000, .v = { 3, 8, }, },
444+
{ 24576000, 352800, .v = { 441, 640, }, },
445+
{ 24576000, 384000, .v = { 3, 4, }, },
446446
};
447447

448448
/* frm_size = 64 */
449449
static const struct cs43130_clk_gen cs43130_64_clk_gen[] = {
450-
{ 22579200, 32000, .v = { 441, 40, }, },
451-
{ 22579200, 44100, .v = { 8, 1, }, },
452-
{ 22579200, 48000, .v = { 147, 20, }, },
453-
{ 22579200, 88200, .v = { 4, 1, }, },
454-
{ 22579200, 96000, .v = { 147, 40, }, },
455-
{ 22579200, 176400, .v = { 2, 1, }, },
456-
{ 22579200, 192000, .v = { 147, 80, }, },
450+
{ 22579200, 32000, .v = { 40, 441, }, },
451+
{ 22579200, 44100, .v = { 1, 8, }, },
452+
{ 22579200, 48000, .v = { 20, 147, }, },
453+
{ 22579200, 88200, .v = { 1, 4, }, },
454+
{ 22579200, 96000, .v = { 40, 147, }, },
455+
{ 22579200, 176400, .v = { 1, 2, }, },
456+
{ 22579200, 192000, .v = { 80, 147, }, },
457457
{ 22579200, 352800, .v = { 1, 1, }, },
458-
{ 24576000, 32000, .v = { 12, 1, }, },
459-
{ 24576000, 44100, .v = { 1280, 147, }, },
460-
{ 24576000, 48000, .v = { 8, 1, }, },
461-
{ 24576000, 88200, .v = { 640, 147, }, },
462-
{ 24576000, 96000, .v = { 4, 1, }, },
463-
{ 24576000, 176400, .v = { 320, 147, }, },
464-
{ 24576000, 192000, .v = { 2, 1, }, },
465-
{ 24576000, 352800, .v = { 160, 147, }, },
458+
{ 24576000, 32000, .v = { 1, 12, }, },
459+
{ 24576000, 44100, .v = { 147, 1280, }, },
460+
{ 24576000, 48000, .v = { 1, 8, }, },
461+
{ 24576000, 88200, .v = { 147, 640, }, },
462+
{ 24576000, 96000, .v = { 1, 4, }, },
463+
{ 24576000, 176400, .v = { 147, 320, }, },
464+
{ 24576000, 192000, .v = { 1, 2, }, },
465+
{ 24576000, 352800, .v = { 147, 160, }, },
466466
{ 24576000, 384000, .v = { 1, 1, }, },
467467
};
468468

‎sound/soc/soc-compress.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -193,6 +193,7 @@ static int soc_compr_open_fe(struct snd_compr_stream *cstream)
193193
snd_soc_dai_compr_shutdown(cpu_dai, cstream, 1);
194194
out:
195195
dpcm_path_put(&list);
196+
snd_soc_dpcm_mutex_unlock(fe);
196197
be_err:
197198
fe->dpcm[stream].runtime_update = SND_SOC_DPCM_UPDATE_NO;
198199
snd_soc_card_mutex_unlock(fe->card);

‎sound/soc/tegra/tegra210_sfc.c‎

Lines changed: 30 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
//
33
// tegra210_sfc.c - Tegra210 SFC driver
44
//
5-
// Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
5+
// Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
66

77
#include <linux/clk.h>
88
#include <linux/device.h>
@@ -42,6 +42,7 @@ static const int tegra210_sfc_rates[TEGRA210_SFC_NUM_RATES] = {
4242
32000,
4343
44100,
4444
48000,
45+
64000,
4546
88200,
4647
96000,
4748
176400,
@@ -2857,6 +2858,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
28572858
coef_8to32,
28582859
coef_8to44,
28592860
coef_8to48,
2861+
UNSUPP_CONV,
28602862
coef_8to88,
28612863
coef_8to96,
28622864
UNSUPP_CONV,
@@ -2872,6 +2874,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
28722874
coef_11to32,
28732875
coef_11to44,
28742876
coef_11to48,
2877+
UNSUPP_CONV,
28752878
coef_11to88,
28762879
coef_11to96,
28772880
UNSUPP_CONV,
@@ -2887,6 +2890,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
28872890
coef_16to32,
28882891
coef_16to44,
28892892
coef_16to48,
2893+
UNSUPP_CONV,
28902894
coef_16to88,
28912895
coef_16to96,
28922896
coef_16to176,
@@ -2902,6 +2906,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
29022906
coef_22to32,
29032907
coef_22to44,
29042908
coef_22to48,
2909+
UNSUPP_CONV,
29052910
coef_22to88,
29062911
coef_22to96,
29072912
coef_22to176,
@@ -2917,6 +2922,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
29172922
coef_24to32,
29182923
coef_24to44,
29192924
coef_24to48,
2925+
UNSUPP_CONV,
29202926
coef_24to88,
29212927
coef_24to96,
29222928
coef_24to176,
@@ -2932,6 +2938,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
29322938
BYPASS_CONV,
29332939
coef_32to44,
29342940
coef_32to48,
2941+
UNSUPP_CONV,
29352942
coef_32to88,
29362943
coef_32to96,
29372944
coef_32to176,
@@ -2947,6 +2954,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
29472954
coef_44to32,
29482955
BYPASS_CONV,
29492956
coef_44to48,
2957+
UNSUPP_CONV,
29502958
coef_44to88,
29512959
coef_44to96,
29522960
coef_44to176,
@@ -2962,11 +2970,28 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
29622970
coef_48to32,
29632971
coef_48to44,
29642972
BYPASS_CONV,
2973+
UNSUPP_CONV,
29652974
coef_48to88,
29662975
coef_48to96,
29672976
coef_48to176,
29682977
coef_48to192,
29692978
},
2979+
/* Convertions from 64 kHz */
2980+
{
2981+
UNSUPP_CONV,
2982+
UNSUPP_CONV,
2983+
UNSUPP_CONV,
2984+
UNSUPP_CONV,
2985+
UNSUPP_CONV,
2986+
UNSUPP_CONV,
2987+
UNSUPP_CONV,
2988+
UNSUPP_CONV,
2989+
UNSUPP_CONV,
2990+
UNSUPP_CONV,
2991+
UNSUPP_CONV,
2992+
UNSUPP_CONV,
2993+
UNSUPP_CONV,
2994+
},
29702995
/* Convertions from 88.2 kHz */
29712996
{
29722997
coef_88to8,
@@ -2977,6 +3002,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
29773002
coef_88to32,
29783003
coef_88to44,
29793004
coef_88to48,
3005+
UNSUPP_CONV,
29803006
BYPASS_CONV,
29813007
coef_88to96,
29823008
coef_88to176,
@@ -2991,6 +3017,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
29913017
coef_96to32,
29923018
coef_96to44,
29933019
coef_96to48,
3020+
UNSUPP_CONV,
29943021
coef_96to88,
29953022
BYPASS_CONV,
29963023
coef_96to176,
@@ -3006,6 +3033,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
30063033
coef_176to32,
30073034
coef_176to44,
30083035
coef_176to48,
3036+
UNSUPP_CONV,
30093037
coef_176to88,
30103038
coef_176to96,
30113039
BYPASS_CONV,
@@ -3021,6 +3049,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
30213049
coef_192to32,
30223050
coef_192to44,
30233051
coef_192to48,
3052+
UNSUPP_CONV,
30243053
coef_192to88,
30253054
coef_192to96,
30263055
coef_192to176,

‎sound/soc/tegra/tegra210_sfc.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
/*
33
* tegra210_sfc.h - Definitions for Tegra210 SFC driver
44
*
5-
* Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
5+
* Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
66
*
77
*/
88

@@ -47,7 +47,7 @@
4747
#define TEGRA210_SFC_EN_SHIFT 0
4848
#define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT)
4949

50-
#define TEGRA210_SFC_NUM_RATES 12
50+
#define TEGRA210_SFC_NUM_RATES 13
5151

5252
/* Fields in TEGRA210_SFC_COEF_RAM */
5353
#define TEGRA210_SFC_COEF_RAM_EN BIT(0)

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