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ZideChen0Peter Zijlstra
ZideChen0
authored and
Peter Zijlstra
committed
perf/x86/intel/uncore: Support IIO free-running counters on DMR
The free-running counters for IIO uncore blocks on Diamond Rapids are similar to Sapphire Rapids IMC freecounters, with the following differences: - The counters are MMIO based. - Only a subset of IP blocks implement free-running counters: HIOP0 (IP Base Addr: 2E7000h) HIOP1 (IP Base Addr: 2EF000h) HIOP3 (IP Base Addr: 2FF000h) HIOP4 (IP Base Addr: 307000h) - IMH2 (Secondary IMH) does not provide free-running counters. Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20251231224233.113839-9-zide.chen@intel.com
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Lines changed: 113 additions & 5 deletions

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‎arch/x86/events/intel/uncore_snbep.c‎

Lines changed: 113 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -472,10 +472,14 @@
472472
#define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e
473473

474474
/* DMR */
475+
#define DMR_IMH1_HIOP_MMIO_BASE 0x1ffff6ae7000
476+
#define DMR_HIOP_MMIO_SIZE 0x8000
475477
#define DMR_CXLCM_EVENT_MASK_EXT 0xf
476478
#define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff
477479
#define DMR_PCIE4_EVENT_MASK_EXT 0xffffff
478480

481+
#define UNCORE_DMR_ITC 0x30
482+
479483
#define DMR_IMC_PMON_FIXED_CTR 0x18
480484
#define DMR_IMC_PMON_FIXED_CTL 0x10
481485

@@ -6442,7 +6446,11 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
64426446
for (node = rb_first(type->boxes); node; node = rb_next(node)) {
64436447
unit = rb_entry(node, struct intel_uncore_discovery_unit, node);
64446448

6445-
if (unit->id > max)
6449+
/*
6450+
* on DMR IMH2, the unit id starts from 0x8000,
6451+
* and we don't need to count it.
6452+
*/
6453+
if ((unit->id > max) && (unit->id < 0x8000))
64466454
max = unit->id;
64476455
}
64486456
return max + 1;
@@ -6930,18 +6938,118 @@ int dmr_uncore_cbb_units_ignore[] = {
69306938
UNCORE_IGNORE_END
69316939
};
69326940

6941+
static unsigned int dmr_iio_freerunning_box_offsets[] = {
6942+
0x0, 0x8000, 0x18000, 0x20000
6943+
};
6944+
6945+
static void dmr_uncore_freerunning_init_box(struct intel_uncore_box *box)
6946+
{
6947+
struct intel_uncore_type *type = box->pmu->type;
6948+
u64 mmio_base;
6949+
6950+
if (box->pmu->pmu_idx >= type->num_boxes)
6951+
return;
6952+
6953+
mmio_base = DMR_IMH1_HIOP_MMIO_BASE;
6954+
mmio_base += dmr_iio_freerunning_box_offsets[box->pmu->pmu_idx];
6955+
6956+
box->io_addr = ioremap(mmio_base, type->mmio_map_size);
6957+
if (!box->io_addr)
6958+
pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
6959+
}
6960+
6961+
static struct intel_uncore_ops dmr_uncore_freerunning_ops = {
6962+
.init_box = dmr_uncore_freerunning_init_box,
6963+
.exit_box = uncore_mmio_exit_box,
6964+
.read_counter = uncore_mmio_read_counter,
6965+
.hw_config = uncore_freerunning_hw_config,
6966+
};
6967+
6968+
enum perf_uncore_dmr_iio_freerunning_type_id {
6969+
DMR_ITC_INB_DATA_BW,
6970+
DMR_ITC_BW_IN,
6971+
DMR_OTC_BW_OUT,
6972+
DMR_OTC_CLOCK_TICKS,
6973+
6974+
DMR_IIO_FREERUNNING_TYPE_MAX,
6975+
};
6976+
6977+
static struct freerunning_counters dmr_iio_freerunning[] = {
6978+
[DMR_ITC_INB_DATA_BW] = { 0x4d40, 0x8, 0, 8, 48},
6979+
[DMR_ITC_BW_IN] = { 0x6b00, 0x8, 0, 8, 48},
6980+
[DMR_OTC_BW_OUT] = { 0x6b60, 0x8, 0, 8, 48},
6981+
[DMR_OTC_CLOCK_TICKS] = { 0x6bb0, 0x8, 0, 1, 48},
6982+
};
6983+
6984+
static struct uncore_event_desc dmr_uncore_iio_freerunning_events[] = {
6985+
/* ITC Free Running Data BW counter for inbound traffic */
6986+
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port0, 0x10, "3.814697266e-6"),
6987+
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port1, 0x11, "3.814697266e-6"),
6988+
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port2, 0x12, "3.814697266e-6"),
6989+
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port3, 0x13, "3.814697266e-6"),
6990+
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port4, 0x14, "3.814697266e-6"),
6991+
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port5, 0x15, "3.814697266e-6"),
6992+
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port6, 0x16, "3.814697266e-6"),
6993+
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port7, 0x17, "3.814697266e-6"),
6994+
6995+
/* ITC Free Running BW IN counters */
6996+
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, "3.814697266e-6"),
6997+
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, "3.814697266e-6"),
6998+
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, "3.814697266e-6"),
6999+
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, "3.814697266e-6"),
7000+
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, "3.814697266e-6"),
7001+
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, "3.814697266e-6"),
7002+
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, "3.814697266e-6"),
7003+
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, "3.814697266e-6"),
7004+
7005+
/* ITC Free Running BW OUT counters */
7006+
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x30, "3.814697266e-6"),
7007+
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x31, "3.814697266e-6"),
7008+
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x32, "3.814697266e-6"),
7009+
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x33, "3.814697266e-6"),
7010+
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port4, 0x34, "3.814697266e-6"),
7011+
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port5, 0x35, "3.814697266e-6"),
7012+
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port6, 0x36, "3.814697266e-6"),
7013+
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port7, 0x37, "3.814697266e-6"),
7014+
7015+
/* Free Running Clock Counter */
7016+
INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x40"),
7017+
{ /* end: all zeroes */ },
7018+
};
7019+
7020+
static struct intel_uncore_type dmr_uncore_iio_free_running = {
7021+
.name = "iio_free_running",
7022+
.num_counters = 25,
7023+
.mmio_map_size = DMR_HIOP_MMIO_SIZE,
7024+
.num_freerunning_types = DMR_IIO_FREERUNNING_TYPE_MAX,
7025+
.freerunning = dmr_iio_freerunning,
7026+
.ops = &dmr_uncore_freerunning_ops,
7027+
.event_descs = dmr_uncore_iio_freerunning_events,
7028+
.format_group = &skx_uncore_iio_freerunning_format_group,
7029+
};
7030+
7031+
#define UNCORE_DMR_MMIO_EXTRA_UNCORES 1
7032+
static struct intel_uncore_type *dmr_mmio_uncores[UNCORE_DMR_MMIO_EXTRA_UNCORES] = {
7033+
&dmr_uncore_iio_free_running,
7034+
};
7035+
69337036
int dmr_uncore_pci_init(void)
69347037
{
69357038
uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL,
69367039
UNCORE_DMR_NUM_UNCORE_TYPES,
69377040
dmr_uncores);
69387041
return 0;
69397042
}
7043+
69407044
void dmr_uncore_mmio_init(void)
69417045
{
6942-
uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL,
6943-
UNCORE_DMR_NUM_UNCORE_TYPES,
6944-
dmr_uncores);
6945-
}
7046+
uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO,
7047+
UNCORE_DMR_MMIO_EXTRA_UNCORES,
7048+
dmr_mmio_uncores,
7049+
UNCORE_DMR_NUM_UNCORE_TYPES,
7050+
dmr_uncores);
69467051

7052+
dmr_uncore_iio_free_running.num_boxes =
7053+
uncore_type_max_boxes(uncore_mmio_uncores, UNCORE_DMR_ITC);
7054+
}
69477055
/* end of DMR uncore support */

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