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Merge tag 'aspeed-5.17-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt
ASPEED device tree updates for 5.17 - New machines: * TYAN S8036 AST2500 BMC * Facebook Bletchley AST2600 BMC * Yadro VEGMAN series of AST2500 BMC for x86 servers - LPC clock additions, to fix long standing missed irq on boot issue - Secure boot controller description for AST2600 - Alternate chip flash layout, used by Bytedance's G220A - Various additions to Rainier, Everest, S7106 * tag 'aspeed-5.17-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: dts: aspeed: add LCLK setting into LPC KCS nodes dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property ARM: dts: aspeed: add LCLK setting into LPC IBT node ARM: dts: aspeed: p10: Add TPM device ARM: dts: aspeed: p10: Enable USB host ports ARM: dts: aspeed: Add TYAN S8036 BMC machine ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config ARM: dts: aspeed: Adding Facebook Bletchley BMC ARM: dts: aspeed: g220a: Enable secondary flash ARM: dts: Add openbmc-flash-layout-64-alt.dtsi ARM: dts: aspeed: Add secure boot controller node dt-bindings: aspeed: Add Secure Boot Controller bindings ARM: dts: aspeed: add device tree for YADRO VEGMAN BMC dt-bindings: vendor-prefixes: add YADRO ARM: dts: aspeed: mtjade: Add uefi partition ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices ARM: dts: aspeed: tyan-s7106: Update nct7802 config Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 862d7e5 + 45cd8bb commit d8db5d8

19 files changed

Lines changed: 2539 additions & 2 deletions

‎Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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# Copyright 2021 Joel Stanley, IBM Corp.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: ASPEED Secure Boot Controller
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maintainers:
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- Joel Stanley <joel@jms.id.au>
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- Andrew Jeffery <andrew@aj.id.au>
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description: |
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The ASPEED SoCs have a register bank for interacting with the secure boot
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controller.
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properties:
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compatible:
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items:
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- const: aspeed,ast2600-sbc
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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sbc: secure-boot-controller@1e6f2000 {
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compatible = "aspeed,ast2600-sbc";
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reg = <0x1e6f2000 0x1000>;
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};

‎Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt‎

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@@ -11,6 +11,7 @@ Required properties:
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"aspeed,ast2500-ibt-bmc"
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"aspeed,ast2600-ibt-bmc"
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- reg: physical address and size of the registers
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- clocks: clock for the device
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Optional properties:
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@@ -23,4 +24,5 @@ Example:
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compatible = "aspeed,ast2400-ibt-bmc";
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reg = <0x1e789140 0x18>;
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interrupts = <8>;
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clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
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};

‎Documentation/devicetree/bindings/vendor-prefixes.yaml‎

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@@ -1356,6 +1356,8 @@ patternProperties:
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description: Shenzhen Xunlong Software CO.,Limited
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"^xylon,.*":
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description: Xylon
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"^yadro,.*":
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description: YADRO
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"^yamaha,.*":
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description: Yamaha Corporation
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"^yes-optoelectronics,.*":

‎arch/arm/boot/dts/Makefile‎

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@@ -1506,6 +1506,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
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aspeed-bmc-arm-stardragon4800-rep2.dtb \
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aspeed-bmc-asrock-e3c246d4i.dtb \
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aspeed-bmc-bytedance-g220a.dtb \
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aspeed-bmc-facebook-bletchley.dtb \
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aspeed-bmc-facebook-cloudripper.dtb \
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aspeed-bmc-facebook-cmm.dtb \
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aspeed-bmc-facebook-elbert.dtb \
@@ -1543,4 +1544,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
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aspeed-bmc-quanta-q71l.dtb \
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aspeed-bmc-supermicro-x11spi.dtb \
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aspeed-bmc-inventec-transformers.dtb \
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aspeed-bmc-tyan-s7106.dtb
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aspeed-bmc-tyan-s7106.dtb \
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aspeed-bmc-tyan-s8036.dtb \
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aspeed-bmc-vegman-n110.dtb \
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aspeed-bmc-vegman-rx20.dtb \
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aspeed-bmc-vegman-sx20.dtb

‎arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts‎

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model = "Ampere Mt. Jade BMC";
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compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
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aliases {
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/*
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* i2c bus 50-57 assigned to NVMe slot 0-7
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*/
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i2c50 = &nvmeslot_0;
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i2c51 = &nvmeslot_1;
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i2c52 = &nvmeslot_2;
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i2c53 = &nvmeslot_3;
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i2c54 = &nvmeslot_4;
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i2c55 = &nvmeslot_5;
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i2c56 = &nvmeslot_6;
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i2c57 = &nvmeslot_7;
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/*
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* i2c bus 60-67 assigned to NVMe slot 8-15
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*/
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i2c60 = &nvmeslot_8;
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i2c61 = &nvmeslot_9;
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i2c62 = &nvmeslot_10;
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i2c63 = &nvmeslot_11;
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i2c64 = &nvmeslot_12;
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i2c65 = &nvmeslot_13;
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i2c66 = &nvmeslot_14;
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i2c67 = &nvmeslot_15;
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/*
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* i2c bus 70-77 assigned to NVMe slot 16-23
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*/
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i2c70 = &nvmeslot_16;
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i2c71 = &nvmeslot_17;
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i2c72 = &nvmeslot_18;
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i2c73 = &nvmeslot_19;
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i2c74 = &nvmeslot_20;
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i2c75 = &nvmeslot_21;
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i2c76 = &nvmeslot_22;
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i2c77 = &nvmeslot_23;
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/*
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* i2c bus 80-81 assigned to NVMe M2 slot 0-1
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*/
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i2c80 = &nvme_m2_0;
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i2c81 = &nvme_m2_1;
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};
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chosen {
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stdout-path = &uart5;
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bootargs = "console=ttyS4,115200 earlycon";
@@ -330,6 +374,15 @@
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m25p,fast-read;
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label = "pnor";
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/* spi-max-frequency = <100000000>; */
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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uefi@400000 {
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reg = <0x400000 0x1C00000>;
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label = "pnor-uefi";
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};
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};
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};
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};
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@@ -445,6 +498,220 @@
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&i2c5 {
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status = "okay";
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i2c-mux@70 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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i2c-mux-idle-disconnect;
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nvmeslot_0_7: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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};
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};
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i2c-mux@71 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x71>;
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i2c-mux-idle-disconnect;
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nvmeslot_8_15: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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};
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nvmeslot_16_23: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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};
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};
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i2c-mux@72 {
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compatible = "nxp,pca9545";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x72>;
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i2c-mux-idle-disconnect;
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nvme_m2_0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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};
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nvme_m2_1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1>;
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};
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};
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};
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&nvmeslot_0_7 {
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status = "okay";
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i2c-mux@75 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c-mux-idle-disconnect;
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nvmeslot_0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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};
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nvmeslot_1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1>;
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};
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nvmeslot_2: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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};
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nvmeslot_3: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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};
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nvmeslot_4: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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};
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nvmeslot_5: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x5>;
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};
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nvmeslot_6: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6>;
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};
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nvmeslot_7: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7>;
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};
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};
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};
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&nvmeslot_8_15 {
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status = "okay";
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i2c-mux@75 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c-mux-idle-disconnect;
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nvmeslot_8: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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};
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nvmeslot_9: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1>;
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};
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nvmeslot_10: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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};
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nvmeslot_11: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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};
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nvmeslot_12: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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};
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nvmeslot_13: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x5>;
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};
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nvmeslot_14: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6>;
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};
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nvmeslot_15: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7>;
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};
661+
};
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};
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664+
&nvmeslot_16_23 {
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status = "okay";
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667+
i2c-mux@75 {
668+
compatible = "nxp,pca9548";
669+
#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c-mux-idle-disconnect;
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nvmeslot_16: i2c@0 {
675+
#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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};
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nvmeslot_17: i2c@1 {
680+
#address-cells = <1>;
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#size-cells = <0>;
682+
reg = <0x1>;
683+
};
684+
nvmeslot_18: i2c@2 {
685+
#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
688+
};
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nvmeslot_19: i2c@3 {
690+
#address-cells = <1>;
691+
#size-cells = <0>;
692+
reg = <0x3>;
693+
};
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nvmeslot_20: i2c@4 {
695+
#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
698+
};
699+
nvmeslot_21: i2c@5 {
700+
#address-cells = <1>;
701+
#size-cells = <0>;
702+
reg = <0x5>;
703+
};
704+
nvmeslot_22: i2c@6 {
705+
#address-cells = <1>;
706+
#size-cells = <0>;
707+
reg = <0x6>;
708+
};
709+
nvmeslot_23: i2c@7 {
710+
#address-cells = <1>;
711+
#size-cells = <0>;
712+
reg = <0x7>;
713+
};
714+
};
448715
};
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&i2c6 {

‎arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts‎

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260260
spi-max-frequency = <50000000>;
261261
#include "openbmc-flash-layout-64.dtsi"
262262
};
263+
flash@1 {
264+
status = "okay";
265+
label = "alt-bmc";
266+
m25p,fast-read;
267+
spi-max-frequency = <50000000>;
268+
#include "openbmc-flash-layout-64-alt.dtsi"
269+
};
263270
};
264271

265272
&spi1 {
@@ -278,6 +285,11 @@
278285
status = "okay";
279286
};
280287

288+
&wdt2 {
289+
status = "okay";
290+
aspeed,alt-boot;
291+
};
292+
281293
&gpio {
282294
status = "okay";
283295
gpio-line-names =

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