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Tao Zhoualexdeucher
Tao Zhou
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alexdeucher
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drm/amdgpu: drop status query/reset for GCEA 9.4.3 and MMEA 1.8
PMFW will be responsible for them. v2: remove query interfaces. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2 files changed

Lines changed: 0 additions & 203 deletions

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‎drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c‎

Lines changed: 0 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -3754,10 +3754,6 @@ static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = {
37543754
AMDGPU_GFX_LDS_MEM, 4},
37553755
};
37563756

3757-
static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = {
3758-
SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
3759-
};
3760-
37613757
static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
37623758
void *ras_error_status, int xcc_id)
37633759
{
@@ -3846,39 +3842,6 @@ static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,
38463842
mutex_unlock(&adev->grbm_idx_mutex);
38473843
}
38483844

3849-
static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev,
3850-
int xcc_id)
3851-
{
3852-
uint32_t i, j;
3853-
uint32_t reg_value;
3854-
3855-
mutex_lock(&adev->grbm_idx_mutex);
3856-
3857-
for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) {
3858-
for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) {
3859-
gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
3860-
reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3861-
regGCEA_ERR_STATUS);
3862-
if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
3863-
REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
3864-
REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
3865-
dev_warn(adev->dev,
3866-
"GCEA err detected at instance: %d, status: 0x%x!\n",
3867-
j, reg_value);
3868-
}
3869-
/* clear after read */
3870-
reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,
3871-
CLEAR_ERROR_STATUS, 0x1);
3872-
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS,
3873-
reg_value);
3874-
}
3875-
}
3876-
3877-
gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3878-
xcc_id);
3879-
mutex_unlock(&adev->grbm_idx_mutex);
3880-
}
3881-
38823845
static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev,
38833846
int xcc_id)
38843847
{
@@ -3983,7 +3946,6 @@ static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev,
39833946
static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev,
39843947
void *ras_error_status, int xcc_id)
39853948
{
3986-
gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id);
39873949
gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id);
39883950
gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id);
39893951
}
@@ -3996,27 +3958,6 @@ static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev,
39963958
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3);
39973959
}
39983960

3999-
static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev,
4000-
int xcc_id)
4001-
{
4002-
uint32_t i, j;
4003-
uint32_t value;
4004-
4005-
mutex_lock(&adev->grbm_idx_mutex);
4006-
for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) {
4007-
for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) {
4008-
gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
4009-
value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS);
4010-
value = REG_SET_FIELD(value, GCEA_ERR_STATUS,
4011-
CLEAR_ERROR_STATUS, 0x1);
4012-
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value);
4013-
}
4014-
}
4015-
gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4016-
xcc_id);
4017-
mutex_unlock(&adev->grbm_idx_mutex);
4018-
}
4019-
40203961
static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev,
40213962
int xcc_id)
40223963
{
@@ -4042,7 +3983,6 @@ static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev,
40423983
void *ras_error_status, int xcc_id)
40433984
{
40443985
gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id);
4045-
gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id);
40463986
gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id);
40473987
}
40483988

‎drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c‎

Lines changed: 0 additions & 143 deletions
Original file line numberDiff line numberDiff line change
@@ -700,152 +700,9 @@ static void mmhub_v1_8_reset_ras_error_count(struct amdgpu_device *adev)
700700
mmhub_v1_8_inst_reset_ras_error_count(adev, i);
701701
}
702702

703-
static const u32 mmhub_v1_8_mmea_err_status_reg[] __maybe_unused = {
704-
regMMEA0_ERR_STATUS,
705-
regMMEA1_ERR_STATUS,
706-
regMMEA2_ERR_STATUS,
707-
regMMEA3_ERR_STATUS,
708-
regMMEA4_ERR_STATUS,
709-
};
710-
711-
static void mmhub_v1_8_inst_query_ras_err_status(struct amdgpu_device *adev,
712-
uint32_t mmhub_inst)
713-
{
714-
uint32_t reg_value;
715-
uint32_t mmea_err_status_addr_dist;
716-
uint32_t i;
717-
718-
/* query mmea ras err status */
719-
mmea_err_status_addr_dist = regMMEA1_ERR_STATUS - regMMEA0_ERR_STATUS;
720-
for (i = 0; i < ARRAY_SIZE(mmhub_v1_8_mmea_err_status_reg); i++) {
721-
reg_value = RREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
722-
regMMEA0_ERR_STATUS,
723-
i * mmea_err_status_addr_dist);
724-
if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
725-
REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
726-
REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
727-
dev_warn(adev->dev,
728-
"Detected MMEA%d err in MMHUB%d, status: 0x%x\n",
729-
i, mmhub_inst, reg_value);
730-
}
731-
}
732-
733-
/* query mm_cane ras err status */
734-
reg_value = RREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ERR_STATUS);
735-
if (REG_GET_FIELD(reg_value, MM_CANE_ERR_STATUS, SDPM_RDRSP_STATUS) ||
736-
REG_GET_FIELD(reg_value, MM_CANE_ERR_STATUS, SDPM_WRRSP_STATUS) ||
737-
REG_GET_FIELD(reg_value, MM_CANE_ERR_STATUS, SDPM_RDRSP_DATAPARITY_ERROR)) {
738-
dev_warn(adev->dev,
739-
"Detected MM CANE err in MMHUB%d, status: 0x%x\n",
740-
mmhub_inst, reg_value);
741-
}
742-
}
743-
744-
static void mmhub_v1_8_query_ras_error_status(struct amdgpu_device *adev)
745-
{
746-
uint32_t inst_mask;
747-
uint32_t i;
748-
749-
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
750-
dev_warn(adev->dev, "MMHUB RAS is not supported\n");
751-
return;
752-
}
753-
754-
inst_mask = adev->aid_mask;
755-
for_each_inst(i, inst_mask)
756-
mmhub_v1_8_inst_query_ras_err_status(adev, i);
757-
}
758-
759-
static void mmhub_v1_8_inst_reset_ras_err_status(struct amdgpu_device *adev,
760-
uint32_t mmhub_inst)
761-
{
762-
uint32_t mmea_cgtt_clk_cntl_addr_dist;
763-
uint32_t mmea_err_status_addr_dist;
764-
uint32_t reg_value;
765-
uint32_t i;
766-
767-
/* reset mmea ras err status */
768-
mmea_cgtt_clk_cntl_addr_dist = regMMEA1_CGTT_CLK_CTRL - regMMEA0_CGTT_CLK_CTRL;
769-
mmea_err_status_addr_dist = regMMEA1_ERR_STATUS - regMMEA0_ERR_STATUS;
770-
for (i = 0; i < ARRAY_SIZE(mmhub_v1_8_mmea_err_status_reg); i++) {
771-
/* force clk branch on for response path
772-
* set MMEA0_CGTT_CLK_CTRL.SOFT_OVERRIDE_RETURN = 1
773-
*/
774-
reg_value = RREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
775-
regMMEA0_CGTT_CLK_CTRL,
776-
i * mmea_cgtt_clk_cntl_addr_dist);
777-
reg_value = REG_SET_FIELD(reg_value, MMEA0_CGTT_CLK_CTRL,
778-
SOFT_OVERRIDE_RETURN, 1);
779-
WREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
780-
regMMEA0_CGTT_CLK_CTRL,
781-
i * mmea_cgtt_clk_cntl_addr_dist,
782-
reg_value);
783-
784-
/* set MMEA0_ERR_STATUS.CLEAR_ERROR_STATUS = 1 */
785-
reg_value = RREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
786-
regMMEA0_ERR_STATUS,
787-
i * mmea_err_status_addr_dist);
788-
reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,
789-
CLEAR_ERROR_STATUS, 1);
790-
WREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
791-
regMMEA0_ERR_STATUS,
792-
i * mmea_err_status_addr_dist,
793-
reg_value);
794-
795-
/* set MMEA0_CGTT_CLK_CTRL.SOFT_OVERRIDE_RETURN = 0 */
796-
reg_value = RREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
797-
regMMEA0_CGTT_CLK_CTRL,
798-
i * mmea_cgtt_clk_cntl_addr_dist);
799-
reg_value = REG_SET_FIELD(reg_value, MMEA0_CGTT_CLK_CTRL,
800-
SOFT_OVERRIDE_RETURN, 0);
801-
WREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
802-
regMMEA0_CGTT_CLK_CTRL,
803-
i * mmea_cgtt_clk_cntl_addr_dist,
804-
reg_value);
805-
}
806-
807-
/* reset mm_cane ras err status
808-
* force clk branch on for response path
809-
* set MM_CANE_ICG_CTRL.SOFT_OVERRIDE_ATRET = 1
810-
*/
811-
reg_value = RREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ICG_CTRL);
812-
reg_value = REG_SET_FIELD(reg_value, MM_CANE_ICG_CTRL,
813-
SOFT_OVERRIDE_ATRET, 1);
814-
WREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ICG_CTRL, reg_value);
815-
816-
/* set MM_CANE_ERR_STATUS.CLEAR_ERROR_STATUS = 1 */
817-
reg_value = RREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ERR_STATUS);
818-
reg_value = REG_SET_FIELD(reg_value, MM_CANE_ERR_STATUS,
819-
CLEAR_ERROR_STATUS, 1);
820-
WREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ERR_STATUS, reg_value);
821-
822-
/* set MM_CANE_ICG_CTRL.SOFT_OVERRIDE_ATRET = 0 */
823-
reg_value = RREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ICG_CTRL);
824-
reg_value = REG_SET_FIELD(reg_value, MM_CANE_ICG_CTRL,
825-
SOFT_OVERRIDE_ATRET, 0);
826-
WREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ICG_CTRL, reg_value);
827-
}
828-
829-
static void mmhub_v1_8_reset_ras_error_status(struct amdgpu_device *adev)
830-
{
831-
uint32_t inst_mask;
832-
uint32_t i;
833-
834-
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
835-
dev_warn(adev->dev, "MMHUB RAS is not supported\n");
836-
return;
837-
}
838-
839-
inst_mask = adev->aid_mask;
840-
for_each_inst(i, inst_mask)
841-
mmhub_v1_8_inst_reset_ras_err_status(adev, i);
842-
}
843-
844703
static const struct amdgpu_ras_block_hw_ops mmhub_v1_8_ras_hw_ops = {
845704
.query_ras_error_count = mmhub_v1_8_query_ras_error_count,
846705
.reset_ras_error_count = mmhub_v1_8_reset_ras_error_count,
847-
.query_ras_error_status = mmhub_v1_8_query_ras_error_status,
848-
.reset_ras_error_status = mmhub_v1_8_reset_ras_error_status,
849706
};
850707

851708
struct amdgpu_mmhub_ras mmhub_v1_8_ras = {

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