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arm64: dts: qcom: sm8650: add GPU nodes
Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Jun Nie <jun.nie@linaro.org> Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-1-206eb0d31694@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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‎arch/arm64/boot/dts/qcom/sm8650.dtsi‎

Lines changed: 181 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2591,6 +2591,143 @@
25912591
#reset-cells = <1>;
25922592
};
25932593

2594+
gpu: gpu@3d00000 {
2595+
compatible = "qcom,adreno-43051401", "qcom,adreno";
2596+
reg = <0x0 0x03d00000 0x0 0x40000>,
2597+
<0x0 0x03d9e000 0x0 0x1000>,
2598+
<0x0 0x03d61000 0x0 0x800>;
2599+
reg-names = "kgsl_3d0_reg_memory",
2600+
"cx_mem",
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"cx_dbgc";
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2603+
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2604+
2605+
iommus = <&adreno_smmu 0 0x0>,
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<&adreno_smmu 1 0x0>;
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operating-points-v2 = <&gpu_opp_table>;
2609+
2610+
qcom,gmu = <&gmu>;
2611+
2612+
status = "disabled";
2613+
2614+
zap-shader {
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memory-region = <&gpu_micro_code_mem>;
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};
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/* Speedbin needs more work on A740+, keep only lower freqs */
2619+
gpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-231000000 {
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opp-hz = /bits/ 64 <231000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
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};
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opp-310000000 {
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opp-hz = /bits/ 64 <310000000>;
2629+
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2630+
};
2631+
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opp-366000000 {
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opp-hz = /bits/ 64 <366000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
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};
2636+
2637+
opp-422000000 {
2638+
opp-hz = /bits/ 64 <422000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2640+
};
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2642+
opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2645+
};
2646+
2647+
opp-578000000 {
2648+
opp-hz = /bits/ 64 <578000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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2652+
opp-629000000 {
2653+
opp-hz = /bits/ 64 <629000000>;
2654+
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
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};
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opp-680000000 {
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opp-hz = /bits/ 64 <680000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
2661+
2662+
opp-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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};
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2667+
opp-770000000 {
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opp-hz = /bits/ 64 <770000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2670+
};
2671+
2672+
opp-834000000 {
2673+
opp-hz = /bits/ 64 <834000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
2676+
};
2677+
};
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2679+
gmu: gmu@3d6a000 {
2680+
compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
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reg = <0x0 0x03d6a000 0x0 0x35000>,
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<0x0 0x03d50000 0x0 0x10000>,
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<0x0 0x0b280000 0x0 0x10000>;
2684+
reg-names = "gmu", "rscc", "gmu_pdc";
2685+
2686+
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2687+
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2688+
interrupt-names = "hfi", "gmu";
2689+
2690+
clocks = <&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
2693+
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
2694+
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2695+
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
2696+
<&gpucc GPU_CC_DEMET_CLK>;
2697+
clock-names = "ahb",
2698+
"gmu",
2699+
"cxo",
2700+
"axi",
2701+
"memnoc",
2702+
"hub",
2703+
"demet";
2704+
2705+
power-domains = <&gpucc GPU_CX_GDSC>,
2706+
<&gpucc GPU_GX_GDSC>;
2707+
power-domain-names = "cx",
2708+
"gx";
2709+
2710+
iommus = <&adreno_smmu 5 0x0>;
2711+
2712+
qcom,qmp = <&aoss_qmp>;
2713+
2714+
operating-points-v2 = <&gmu_opp_table>;
2715+
2716+
gmu_opp_table: opp-table {
2717+
compatible = "operating-points-v2";
2718+
2719+
opp-260000000 {
2720+
opp-hz = /bits/ 64 <260000000>;
2721+
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2722+
};
2723+
2724+
opp-625000000 {
2725+
opp-hz = /bits/ 64 <625000000>;
2726+
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2727+
};
2728+
};
2729+
};
2730+
25942731
gpucc: clock-controller@3d90000 {
25952732
compatible = "qcom,sm8650-gpucc";
25962733
reg = <0 0x03d90000 0 0xa000>;
@@ -2604,6 +2741,50 @@
26042741
#power-domain-cells = <1>;
26052742
};
26062743

2744+
adreno_smmu: iommu@3da0000 {
2745+
compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
2746+
"qcom,smmu-500", "arm,mmu-500";
2747+
reg = <0x0 0x03da0000 0x0 0x40000>;
2748+
#iommu-cells = <2>;
2749+
#global-interrupts = <1>;
2750+
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2751+
<GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
2752+
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2753+
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2754+
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2755+
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2756+
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2757+
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2758+
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2759+
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2760+
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2761+
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2762+
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2763+
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2764+
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2765+
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2766+
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2767+
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2768+
<GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2769+
<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2770+
<GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2771+
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2772+
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2773+
<GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2774+
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2775+
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
2776+
clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2777+
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2778+
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2779+
<&gpucc GPU_CC_AHB_CLK>;
2780+
clock-names = "hlos",
2781+
"bus",
2782+
"iface",
2783+
"ahb";
2784+
power-domains = <&gpucc GPU_CX_GDSC>;
2785+
dma-coherent;
2786+
};
2787+
26072788
ipa: ipa@3f40000 {
26082789
compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
26092790

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