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Hawking Zhangalexdeucher
Hawking Zhang
authored and
alexdeucher
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drm/amdgpu: switch to v9_4_3 gfx_funcs callbacks for GC 9.4.3
add gfx_funcs callbacks implemenation based on gc_v9_4_3 ip headers Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent ca9beb8 commit de7511a

2 files changed

Lines changed: 126 additions & 29 deletions

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‎drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c‎

Lines changed: 125 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#include "amdgpu_gfx.h"
2727
#include "soc15.h"
2828
#include "soc15_common.h"
29+
#include "vega10_enum.h"
2930

3031
#include "gc/gc_9_4_3_offset.h"
3132
#include "gc/gc_9_4_3_sh_mask.h"
@@ -34,6 +35,121 @@
3435

3536
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
3637

38+
static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
39+
{
40+
uint64_t clock;
41+
42+
amdgpu_gfx_off_ctrl(adev, false);
43+
mutex_lock(&adev->gfx.gpu_clock_mutex);
44+
WREG32_SOC15(GC, 0, regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
45+
clock = (uint64_t)RREG32_SOC15(GC, 0, regRLC_GPU_CLOCK_COUNT_LSB) |
46+
((uint64_t)RREG32_SOC15(GC, 0, regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
47+
mutex_unlock(&adev->gfx.gpu_clock_mutex);
48+
amdgpu_gfx_off_ctrl(adev, true);
49+
50+
return clock;
51+
}
52+
53+
static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev,
54+
u32 se_num,
55+
u32 sh_num,
56+
u32 instance)
57+
{
58+
u32 data;
59+
60+
if (instance == 0xffffffff)
61+
data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
62+
INSTANCE_BROADCAST_WRITES, 1);
63+
else
64+
data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
65+
INSTANCE_INDEX, instance);
66+
67+
if (se_num == 0xffffffff)
68+
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
69+
SE_BROADCAST_WRITES, 1);
70+
else
71+
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
72+
73+
if (sh_num == 0xffffffff)
74+
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
75+
SH_BROADCAST_WRITES, 1);
76+
else
77+
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
78+
79+
WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);
80+
}
81+
82+
static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
83+
{
84+
WREG32_SOC15_RLC(GC, 0, regSQ_IND_INDEX,
85+
(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
86+
(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
87+
(address << SQ_IND_INDEX__INDEX__SHIFT) |
88+
(SQ_IND_INDEX__FORCE_READ_MASK));
89+
return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
90+
}
91+
92+
static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
93+
uint32_t wave, uint32_t thread,
94+
uint32_t regno, uint32_t num, uint32_t *out)
95+
{
96+
WREG32_SOC15_RLC(GC, 0, regSQ_IND_INDEX,
97+
(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
98+
(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
99+
(regno << SQ_IND_INDEX__INDEX__SHIFT) |
100+
(thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
101+
(SQ_IND_INDEX__FORCE_READ_MASK) |
102+
(SQ_IND_INDEX__AUTO_INCR_MASK));
103+
while (num--)
104+
*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
105+
}
106+
107+
static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev,
108+
uint32_t simd, uint32_t wave,
109+
uint32_t *dst, int *no_fields)
110+
{
111+
/* type 1 wave data */
112+
dst[(*no_fields)++] = 1;
113+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
114+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
115+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
116+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
117+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
118+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
119+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
120+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
121+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
122+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
123+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
124+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
125+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
126+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
127+
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
128+
}
129+
130+
static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
131+
uint32_t wave, uint32_t start,
132+
uint32_t size, uint32_t *dst)
133+
{
134+
wave_read_regs(adev, simd, wave, 0,
135+
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
136+
}
137+
138+
static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
139+
uint32_t wave, uint32_t thread,
140+
uint32_t start, uint32_t size,
141+
uint32_t *dst)
142+
{
143+
wave_read_regs(adev, simd, wave, thread,
144+
start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
145+
}
146+
147+
static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
148+
u32 me, u32 pipe, u32 q, u32 vm)
149+
{
150+
soc15_grbm_select(adev, me, pipe, q, vm);
151+
}
152+
37153
static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
38154
{
39155
uint32_t rlc_setting;
@@ -80,35 +196,6 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
80196
return 0;
81197
}
82198

83-
static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev,
84-
u32 se_num,
85-
u32 sh_num,
86-
u32 instance)
87-
{
88-
u32 data;
89-
90-
if (instance == 0xffffffff)
91-
data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
92-
INSTANCE_BROADCAST_WRITES, 1);
93-
else
94-
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
95-
instance);
96-
97-
if (se_num == 0xffffffff)
98-
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
99-
1);
100-
else
101-
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
102-
103-
if (sh_num == 0xffffffff)
104-
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
105-
1);
106-
else
107-
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
108-
109-
WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);
110-
}
111-
112199
static void gfx_v9_4_3_wait_for_rlc_serdes(struct amdgpu_device *adev)
113200
{
114201
u32 i, j, k;
@@ -320,6 +407,15 @@ static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offs
320407
ARRAY_SIZE(rlcg_access_gc_9_4_3));
321408
}
322409

410+
const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
411+
.get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
412+
.select_se_sh = &gfx_v9_4_3_select_se_sh,
413+
.read_wave_data = &gfx_v9_4_3_read_wave_data,
414+
.read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
415+
.read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
416+
.select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
417+
};
418+
323419
const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
324420
.is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
325421
.set_safe_mode = gfx_v9_4_3_set_safe_mode,

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
2424
#ifndef __GFX_V9_4_3_H__
2525
#define __GFX_V9_4_3_H__
2626

27+
extern const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs;
2728
extern const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs;
2829

2930
#endif /* __GFX_V9_4_3_H__ */

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