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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon: "ACPI: - Improve error reporting when failing to manage SDEI on AGDI device removal Assembly routines: - Improve register constraints so that the compiler can make use of the zero register instead of moving an immediate #0 into a GPR - Allow the compiler to allocate the registers used for CAS instructions CPU features and system registers: - Cleanups to the way in which CPU features are identified from the ID register fields - Extend system register definition generation to handle Enum types when defining shared register fields - Generate definitions for new _EL2 registers and add new fields for ID_AA64PFR1_EL1 - Allow SVE to be disabled separately from SME on the kernel command-line Tracing: - Support for "direct calls" in ftrace, which enables BPF tracing for arm64 Kdump: - Don't bother unmapping the crashkernel from the linear mapping, which then allows us to use huge (block) mappings and reduce TLB pressure when a crashkernel is loaded. Memory management: - Try again to remove data cache invalidation from the coherent DMA allocation path - Simplify the fixmap code by mapping at page granularity - Allow the kfence pool to be allocated early, preventing the rest of the linear mapping from being forced to page granularity Perf and PMU: - Move CPU PMU code out to drivers/perf/ where it can be reused by the 32-bit ARM architecture when running on ARMv8 CPUs - Fix race between CPU PMU probing and pKVM host de-privilege - Add support for Apple M2 CPU PMU - Adjust the generic PERF_COUNT_HW_BRANCH_INSTRUCTIONS event dynamically, depending on what the CPU actually supports - Minor fixes and cleanups to system PMU drivers Stack tracing: - Use the XPACLRI instruction to strip PAC from pointers, rather than rolling our own function in C - Remove redundant PAC removal for toolchains that handle this in their builtins - Make backtracing more resilient in the face of instrumentation Miscellaneous: - Fix single-step with KGDB - Remove harmless warning when 'nokaslr' is passed on the kernel command-line - Minor fixes and cleanups across the board" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (72 commits) KVM: arm64: Ensure CPU PMU probes before pKVM host de-privilege arm64: kexec: include reboot.h arm64: delete dead code in this_cpu_set_vectors() arm64/cpufeature: Use helper macro to specify ID register for capabilites drivers/perf: hisi: add NULL check for name drivers/perf: hisi: Remove redundant initialized of pmu->name arm64/cpufeature: Consistently use symbolic constants for min_field_value arm64/cpufeature: Pull out helper for CPUID register definitions arm64/sysreg: Convert HFGITR_EL2 to automatic generation ACPI: AGDI: Improve error reporting for problems during .remove() arm64: kernel: Fix kernel warning when nokaslr is passed to commandline perf/arm-cmn: Fix port detection for CMN-700 arm64: kgdb: Set PSTATE.SS to 1 to re-enable single-step arm64: move PAC masks to <asm/pointer_auth.h> arm64: use XPACLRI to strip PAC arm64: avoid redundant PAC stripping in __builtin_return_address() arm64/sme: Fix some comments of ARM SME arm64/signal: Alloc tpidr2 sigframe after checking system_supports_tpidr2() arm64/signal: Use system_supports_tpidr2() to check TPIDR2 arm64/idreg: Don't disable SME when disabling SVE ...
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Lines changed: 1936 additions & 1725 deletions

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‎Documentation/devicetree/bindings/arm/pmu.yaml‎

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@@ -20,6 +20,8 @@ properties:
2020
items:
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- enum:
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- apm,potenza-pmu
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- apple,avalanche-pmu
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- apple,blizzard-pmu
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- apple,firestorm-pmu
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- apple,icestorm-pmu
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- arm,armv8-pmuv3 # Only for s/w models

‎arch/arm/include/asm/arm_pmuv3.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_PMUV3_H
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#define __ASM_PMUV3_H
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#define PMCCNTR __ACCESS_CP15_64(0, c9)
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#define PMCR __ACCESS_CP15(c9, 0, c12, 0)
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#define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1)
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#define PMCNTENCLR __ACCESS_CP15(c9, 0, c12, 2)
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#define PMOVSR __ACCESS_CP15(c9, 0, c12, 3)
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#define PMSELR __ACCESS_CP15(c9, 0, c12, 5)
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#define PMCEID0 __ACCESS_CP15(c9, 0, c12, 6)
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#define PMCEID1 __ACCESS_CP15(c9, 0, c12, 7)
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#define PMXEVTYPER __ACCESS_CP15(c9, 0, c13, 1)
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#define PMXEVCNTR __ACCESS_CP15(c9, 0, c13, 2)
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#define PMUSERENR __ACCESS_CP15(c9, 0, c14, 0)
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#define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1)
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#define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2)
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#define PMMIR __ACCESS_CP15(c9, 0, c14, 6)
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#define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7)
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#define PMEVCNTR0 __ACCESS_CP15(c14, 0, c8, 0)
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#define PMEVCNTR1 __ACCESS_CP15(c14, 0, c8, 1)
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#define PMEVCNTR2 __ACCESS_CP15(c14, 0, c8, 2)
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#define PMEVCNTR3 __ACCESS_CP15(c14, 0, c8, 3)
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#define PMEVCNTR4 __ACCESS_CP15(c14, 0, c8, 4)
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#define PMEVCNTR5 __ACCESS_CP15(c14, 0, c8, 5)
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#define PMEVCNTR6 __ACCESS_CP15(c14, 0, c8, 6)
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#define PMEVCNTR7 __ACCESS_CP15(c14, 0, c8, 7)
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#define PMEVCNTR8 __ACCESS_CP15(c14, 0, c9, 0)
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#define PMEVCNTR9 __ACCESS_CP15(c14, 0, c9, 1)
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#define PMEVCNTR10 __ACCESS_CP15(c14, 0, c9, 2)
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#define PMEVCNTR11 __ACCESS_CP15(c14, 0, c9, 3)
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#define PMEVCNTR12 __ACCESS_CP15(c14, 0, c9, 4)
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#define PMEVCNTR13 __ACCESS_CP15(c14, 0, c9, 5)
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#define PMEVCNTR14 __ACCESS_CP15(c14, 0, c9, 6)
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#define PMEVCNTR15 __ACCESS_CP15(c14, 0, c9, 7)
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#define PMEVCNTR16 __ACCESS_CP15(c14, 0, c10, 0)
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#define PMEVCNTR17 __ACCESS_CP15(c14, 0, c10, 1)
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#define PMEVCNTR18 __ACCESS_CP15(c14, 0, c10, 2)
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#define PMEVCNTR19 __ACCESS_CP15(c14, 0, c10, 3)
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#define PMEVCNTR20 __ACCESS_CP15(c14, 0, c10, 4)
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#define PMEVCNTR21 __ACCESS_CP15(c14, 0, c10, 5)
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#define PMEVCNTR22 __ACCESS_CP15(c14, 0, c10, 6)
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#define PMEVCNTR23 __ACCESS_CP15(c14, 0, c10, 7)
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#define PMEVCNTR24 __ACCESS_CP15(c14, 0, c11, 0)
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#define PMEVCNTR25 __ACCESS_CP15(c14, 0, c11, 1)
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#define PMEVCNTR26 __ACCESS_CP15(c14, 0, c11, 2)
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#define PMEVCNTR27 __ACCESS_CP15(c14, 0, c11, 3)
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#define PMEVCNTR28 __ACCESS_CP15(c14, 0, c11, 4)
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#define PMEVCNTR29 __ACCESS_CP15(c14, 0, c11, 5)
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#define PMEVCNTR30 __ACCESS_CP15(c14, 0, c11, 6)
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#define PMEVTYPER0 __ACCESS_CP15(c14, 0, c12, 0)
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#define PMEVTYPER1 __ACCESS_CP15(c14, 0, c12, 1)
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#define PMEVTYPER2 __ACCESS_CP15(c14, 0, c12, 2)
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#define PMEVTYPER3 __ACCESS_CP15(c14, 0, c12, 3)
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#define PMEVTYPER4 __ACCESS_CP15(c14, 0, c12, 4)
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#define PMEVTYPER5 __ACCESS_CP15(c14, 0, c12, 5)
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#define PMEVTYPER6 __ACCESS_CP15(c14, 0, c12, 6)
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#define PMEVTYPER7 __ACCESS_CP15(c14, 0, c12, 7)
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#define PMEVTYPER8 __ACCESS_CP15(c14, 0, c13, 0)
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#define PMEVTYPER9 __ACCESS_CP15(c14, 0, c13, 1)
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#define PMEVTYPER10 __ACCESS_CP15(c14, 0, c13, 2)
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#define PMEVTYPER11 __ACCESS_CP15(c14, 0, c13, 3)
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#define PMEVTYPER12 __ACCESS_CP15(c14, 0, c13, 4)
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#define PMEVTYPER13 __ACCESS_CP15(c14, 0, c13, 5)
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#define PMEVTYPER14 __ACCESS_CP15(c14, 0, c13, 6)
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#define PMEVTYPER15 __ACCESS_CP15(c14, 0, c13, 7)
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#define PMEVTYPER16 __ACCESS_CP15(c14, 0, c14, 0)
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#define PMEVTYPER17 __ACCESS_CP15(c14, 0, c14, 1)
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#define PMEVTYPER18 __ACCESS_CP15(c14, 0, c14, 2)
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#define PMEVTYPER19 __ACCESS_CP15(c14, 0, c14, 3)
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#define PMEVTYPER20 __ACCESS_CP15(c14, 0, c14, 4)
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#define PMEVTYPER21 __ACCESS_CP15(c14, 0, c14, 5)
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#define PMEVTYPER22 __ACCESS_CP15(c14, 0, c14, 6)
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#define PMEVTYPER23 __ACCESS_CP15(c14, 0, c14, 7)
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#define PMEVTYPER24 __ACCESS_CP15(c14, 0, c15, 0)
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#define PMEVTYPER25 __ACCESS_CP15(c14, 0, c15, 1)
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#define PMEVTYPER26 __ACCESS_CP15(c14, 0, c15, 2)
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#define PMEVTYPER27 __ACCESS_CP15(c14, 0, c15, 3)
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#define PMEVTYPER28 __ACCESS_CP15(c14, 0, c15, 4)
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#define PMEVTYPER29 __ACCESS_CP15(c14, 0, c15, 5)
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#define PMEVTYPER30 __ACCESS_CP15(c14, 0, c15, 6)
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#define RETURN_READ_PMEVCNTRN(n) \
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return read_sysreg(PMEVCNTR##n)
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static unsigned long read_pmevcntrn(int n)
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{
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PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
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return 0;
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}
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#define WRITE_PMEVCNTRN(n) \
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write_sysreg(val, PMEVCNTR##n)
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static void write_pmevcntrn(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
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}
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#define WRITE_PMEVTYPERN(n) \
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write_sysreg(val, PMEVTYPER##n)
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static void write_pmevtypern(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
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}
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static inline unsigned long read_pmmir(void)
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{
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return read_sysreg(PMMIR);
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}
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static inline u32 read_pmuver(void)
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{
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/* PMUVers is not a signed field */
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u32 dfr0 = read_cpuid_ext(CPUID_EXT_DFR0);
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return (dfr0 >> 24) & 0xf;
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}
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static inline void write_pmcr(u32 val)
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{
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write_sysreg(val, PMCR);
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}
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static inline u32 read_pmcr(void)
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{
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return read_sysreg(PMCR);
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}
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static inline void write_pmselr(u32 val)
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{
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write_sysreg(val, PMSELR);
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}
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static inline void write_pmccntr(u64 val)
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{
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write_sysreg(val, PMCCNTR);
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}
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static inline u64 read_pmccntr(void)
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{
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return read_sysreg(PMCCNTR);
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}
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static inline void write_pmxevcntr(u32 val)
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{
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write_sysreg(val, PMXEVCNTR);
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}
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static inline u32 read_pmxevcntr(void)
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{
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return read_sysreg(PMXEVCNTR);
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}
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static inline void write_pmxevtyper(u32 val)
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{
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write_sysreg(val, PMXEVTYPER);
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}
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static inline void write_pmcntenset(u32 val)
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{
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write_sysreg(val, PMCNTENSET);
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}
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static inline void write_pmcntenclr(u32 val)
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{
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write_sysreg(val, PMCNTENCLR);
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}
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static inline void write_pmintenset(u32 val)
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{
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write_sysreg(val, PMINTENSET);
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}
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static inline void write_pmintenclr(u32 val)
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{
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write_sysreg(val, PMINTENCLR);
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}
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static inline void write_pmccfiltr(u32 val)
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{
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write_sysreg(val, PMCCFILTR);
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}
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static inline void write_pmovsclr(u32 val)
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{
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write_sysreg(val, PMOVSR);
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}
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static inline u32 read_pmovsclr(void)
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{
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return read_sysreg(PMOVSR);
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}
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static inline void write_pmuserenr(u32 val)
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{
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write_sysreg(val, PMUSERENR);
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}
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static inline u32 read_pmceid0(void)
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{
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return read_sysreg(PMCEID0);
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}
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static inline u32 read_pmceid1(void)
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{
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return read_sysreg(PMCEID1);
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}
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static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
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static inline void kvm_clr_pmu_events(u32 clr) {}
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static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
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{
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return false;
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}
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/* PMU Version in DFR Register */
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#define ARMV8_PMU_DFR_VER_NI 0
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#define ARMV8_PMU_DFR_VER_V3P4 0x5
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#define ARMV8_PMU_DFR_VER_V3P5 0x6
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#define ARMV8_PMU_DFR_VER_IMP_DEF 0xF
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static inline bool pmuv3_implemented(int pmuver)
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{
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return !(pmuver == ARMV8_PMU_DFR_VER_IMP_DEF ||
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pmuver == ARMV8_PMU_DFR_VER_NI);
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}
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static inline bool is_pmuv3p4(int pmuver)
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{
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return pmuver >= ARMV8_PMU_DFR_VER_V3P4;
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}
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static inline bool is_pmuv3p5(int pmuver)
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{
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return pmuver >= ARMV8_PMU_DFR_VER_V3P5;
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}
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#endif

‎arch/arm/mm/Kconfig‎

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select CPU_THUMB_CAPABLE
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select CPU_TLB_V6 if MMU
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# ARMv7
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# ARMv7 and ARMv8 architectures
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config CPU_V7
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bool
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select CPU_32v6K

‎arch/arm64/Kconfig‎

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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DMA_CONTIGUOUS
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select HAVE_DYNAMIC_FTRACE
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select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
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if $(cc-option,-fpatchable-function-entry=2)
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select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
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if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
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select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
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if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
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!CC_OPTIMIZE_FOR_SIZE)
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config BROKEN_GAS_INST
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def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
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config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
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bool
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# Clang's __builtin_return_adddress() strips the PAC since 12.0.0
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# https://reviews.llvm.org/D75044
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default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)
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# GCC's __builtin_return_address() strips the PAC since 11.1.0,
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# and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
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# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
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default y if CC_IS_GCC && (GCC_VERSION >= 110100)
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default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
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default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000)
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default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000)
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default n
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config KASAN_SHADOW_OFFSET
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hex
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depends on KASAN_GENERIC || KASAN_SW_TAGS

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