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Merge tag 'renesas-fixes-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v5.14 - Fix a clock/reset handling design issue on the new RZ/G2L SoC, requiring an atomic change to DT binding definitions, clock driver, and DTS, - Restore graphical consoles in the shmobile_defconfig. * tag 'renesas-fixes-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: shmobile: defconfig: Restore graphical consoles dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions clk: renesas: r9a07g044: Add P2 Clock support clk: renesas: r9a07g044: Fix P1 Clock clk: renesas: r9a07g044: Rename divider table clk: renesas: rzg2l: Add multi clock PM support Link: https://lore.kernel.org/r/cover.1626253929.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents b6e473d + 432b52e commit e0129a0

6 files changed

Lines changed: 320 additions & 147 deletions

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‎arch/arm/configs/shmobile_defconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,7 @@ CONFIG_DRM_SII902X=y
135135
CONFIG_DRM_SIMPLE_BRIDGE=y
136136
CONFIG_DRM_I2C_ADV7511=y
137137
CONFIG_DRM_I2C_ADV7511_AUDIO=y
138+
CONFIG_FB=y
138139
CONFIG_FB_SH_MOBILE_LCDC=y
139140
CONFIG_BACKLIGHT_PWM=y
140141
CONFIG_BACKLIGHT_AS3711=y

‎arch/arm64/boot/dts/renesas/r9a07g044.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,10 +82,10 @@
8282
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
8383
interrupt-names = "eri", "rxi", "txi",
8484
"bri", "dri", "tei";
85-
clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
85+
clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
8686
clock-names = "fck";
8787
power-domains = <&cpg>;
88-
resets = <&cpg R9A07G044_CLK_SCIF0>;
88+
resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
8989
status = "disabled";
9090
};
9191

‎drivers/clk/renesas/r9a07g044-cpg.c‎

Lines changed: 47 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,9 @@ enum clk_ids {
3030
CLK_PLL2_DIV20,
3131
CLK_PLL3,
3232
CLK_PLL3_DIV2,
33+
CLK_PLL3_DIV2_4,
34+
CLK_PLL3_DIV2_4_2,
3335
CLK_PLL3_DIV4,
34-
CLK_PLL3_DIV8,
3536
CLK_PLL4,
3637
CLK_PLL5,
3738
CLK_PLL5_DIV2,
@@ -42,12 +43,13 @@ enum clk_ids {
4243
};
4344

4445
/* Divider tables */
45-
static const struct clk_div_table dtable_3b[] = {
46+
static const struct clk_div_table dtable_1_32[] = {
4647
{0, 1},
4748
{1, 2},
4849
{2, 4},
4950
{3, 8},
5051
{4, 32},
52+
{0, 0},
5153
};
5254

5355
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
@@ -66,47 +68,56 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
6668
DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
6769

6870
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
71+
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
72+
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
6973
DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
70-
DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
7174

7275
/* Core output clk */
7376
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
7477
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
75-
dtable_3b, CLK_DIVIDER_HIWORD_MASK),
78+
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
7679
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
77-
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
78-
DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
80+
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
81+
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
82+
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
83+
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
7984
};
8085

8186
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
82-
DEF_MOD("gic", R9A07G044_CLK_GIC600,
83-
R9A07G044_CLK_P1,
84-
0x514, BIT(0), (BIT(0) | BIT(1))),
85-
DEF_MOD("ia55", R9A07G044_CLK_IA55,
86-
R9A07G044_CLK_P1,
87-
0x518, (BIT(0) | BIT(1)), BIT(0)),
88-
DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
89-
R9A07G044_CLK_P0,
90-
0x584, BIT(0), BIT(0)),
91-
DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
92-
R9A07G044_CLK_P0,
93-
0x584, BIT(1), BIT(1)),
94-
DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
95-
R9A07G044_CLK_P0,
96-
0x584, BIT(2), BIT(2)),
97-
DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
98-
R9A07G044_CLK_P0,
99-
0x584, BIT(3), BIT(3)),
100-
DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
101-
R9A07G044_CLK_P0,
102-
0x584, BIT(4), BIT(4)),
103-
DEF_MOD("sci0", R9A07G044_CLK_SCI0,
104-
R9A07G044_CLK_P0,
105-
0x588, BIT(0), BIT(0)),
87+
DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
88+
0x514, 0),
89+
DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
90+
0x518, 0),
91+
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
92+
0x518, 1),
93+
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
94+
0x584, 0),
95+
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
96+
0x584, 1),
97+
DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
98+
0x584, 2),
99+
DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
100+
0x584, 3),
101+
DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
102+
0x584, 4),
103+
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
104+
0x588, 0),
105+
};
106+
107+
static struct rzg2l_reset r9a07g044_resets[] = {
108+
DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
109+
DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
110+
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
111+
DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
112+
DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
113+
DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
114+
DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
115+
DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
116+
DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
106117
};
107118

108119
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
109-
MOD_CLK_BASE + R9A07G044_CLK_GIC600,
120+
MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
110121
};
111122

112123
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
@@ -123,5 +134,9 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
123134
/* Module Clocks */
124135
.mod_clks = r9a07g044_mod_clks,
125136
.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
126-
.num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
137+
.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
138+
139+
/* Resets */
140+
.resets = r9a07g044_resets,
141+
.num_resets = ARRAY_SIZE(r9a07g044_resets),
127142
};

‎drivers/clk/renesas/renesas-rzg2l-cpg.c‎

Lines changed: 59 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,9 @@
4747
#define SDIV(val) DIV_RSMASK(val, 0, 0x7)
4848

4949
#define CLK_ON_R(reg) (reg)
50-
#define CLK_MON_R(reg) (0x680 - 0x500 + (reg))
51-
#define CLK_RST_R(reg) (0x800 - 0x500 + (reg))
52-
#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg))
50+
#define CLK_MON_R(reg) (0x180 + (reg))
51+
#define CLK_RST_R(reg) (reg)
52+
#define CLK_MRST_R(reg) (0x180 + (reg))
5353

5454
#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
5555
#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
@@ -78,6 +78,7 @@ struct rzg2l_cpg_priv {
7878
struct clk **clks;
7979
unsigned int num_core_clks;
8080
unsigned int num_mod_clks;
81+
unsigned int num_resets;
8182
unsigned int last_dt_core_clk;
8283

8384
struct raw_notifier_head notifiers;
@@ -315,15 +316,13 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
315316
*
316317
* @hw: handle between common and hardware-specific interfaces
317318
* @off: register offset
318-
* @onoff: ON/MON bits
319-
* @reset: reset bits
319+
* @bit: ON/MON bit
320320
* @priv: CPG/MSTP private data
321321
*/
322322
struct mstp_clock {
323323
struct clk_hw hw;
324324
u16 off;
325-
u8 onoff;
326-
u8 reset;
325+
u8 bit;
327326
struct rzg2l_cpg_priv *priv;
328327
};
329328

@@ -337,6 +336,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
337336
struct device *dev = priv->dev;
338337
unsigned long flags;
339338
unsigned int i;
339+
u32 bitmask = BIT(clock->bit);
340340
u32 value;
341341

342342
if (!clock->off) {
@@ -349,9 +349,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
349349
spin_lock_irqsave(&priv->rmw_lock, flags);
350350

351351
if (enable)
352-
value = (clock->onoff << 16) | clock->onoff;
352+
value = (bitmask << 16) | bitmask;
353353
else
354-
value = clock->onoff << 16;
354+
value = bitmask << 16;
355355
writel(value, priv->base + CLK_ON_R(reg));
356356

357357
spin_unlock_irqrestore(&priv->rmw_lock, flags);
@@ -360,7 +360,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
360360
return 0;
361361

362362
for (i = 1000; i > 0; --i) {
363-
if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff))
363+
if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
364364
break;
365365
cpu_relax();
366366
}
@@ -388,6 +388,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
388388
{
389389
struct mstp_clock *clock = to_mod_clock(hw);
390390
struct rzg2l_cpg_priv *priv = clock->priv;
391+
u32 bitmask = BIT(clock->bit);
391392
u32 value;
392393

393394
if (!clock->off) {
@@ -397,7 +398,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
397398

398399
value = readl(priv->base + CLK_MON_R(clock->off));
399400

400-
return !(value & clock->onoff);
401+
return !(value & bitmask);
401402
}
402403

403404
static const struct clk_ops rzg2l_mod_clock_ops = {
@@ -457,8 +458,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
457458
init.num_parents = 1;
458459

459460
clock->off = mod->off;
460-
clock->onoff = mod->onoff;
461-
clock->reset = mod->reset;
461+
clock->bit = mod->bit;
462462
clock->priv = priv;
463463
clock->hw.init = &init;
464464

@@ -483,12 +483,11 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
483483
{
484484
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
485485
const struct rzg2l_cpg_info *info = priv->info;
486-
unsigned int reg = info->mod_clks[id].off;
487-
u32 dis = info->mod_clks[id].reset;
486+
unsigned int reg = info->resets[id].off;
487+
u32 dis = BIT(info->resets[id].bit);
488488
u32 we = dis << 16;
489489

490-
dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n",
491-
info->mod_clks[id].name, id, CLK_RST_R(reg));
490+
dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
492491

493492
/* Reset module */
494493
writel(we, priv->base + CLK_RST_R(reg));
@@ -507,11 +506,10 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
507506
{
508507
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
509508
const struct rzg2l_cpg_info *info = priv->info;
510-
unsigned int reg = info->mod_clks[id].off;
511-
u32 value = info->mod_clks[id].reset << 16;
509+
unsigned int reg = info->resets[id].off;
510+
u32 value = BIT(info->resets[id].bit) << 16;
512511

513-
dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n",
514-
info->mod_clks[id].name, id, CLK_RST_R(reg));
512+
dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
515513

516514
writel(value, priv->base + CLK_RST_R(reg));
517515
return 0;
@@ -522,12 +520,12 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
522520
{
523521
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
524522
const struct rzg2l_cpg_info *info = priv->info;
525-
unsigned int reg = info->mod_clks[id].off;
526-
u32 dis = info->mod_clks[id].reset;
523+
unsigned int reg = info->resets[id].off;
524+
u32 dis = BIT(info->resets[id].bit);
527525
u32 value = (dis << 16) | dis;
528526

529-
dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n",
530-
info->mod_clks[id].name, id, CLK_RST_R(reg));
527+
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
528+
CLK_RST_R(reg));
531529

532530
writel(value, priv->base + CLK_RST_R(reg));
533531
return 0;
@@ -538,8 +536,8 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
538536
{
539537
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
540538
const struct rzg2l_cpg_info *info = priv->info;
541-
unsigned int reg = info->mod_clks[id].off;
542-
u32 bitmask = info->mod_clks[id].reset;
539+
unsigned int reg = info->resets[id].off;
540+
u32 bitmask = BIT(info->resets[id].bit);
543541

544542
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
545543
}
@@ -554,9 +552,11 @@ static const struct reset_control_ops rzg2l_cpg_reset_ops = {
554552
static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
555553
const struct of_phandle_args *reset_spec)
556554
{
555+
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
556+
const struct rzg2l_cpg_info *info = priv->info;
557557
unsigned int id = reset_spec->args[0];
558558

559-
if (id >= rcdev->nr_resets) {
559+
if (id >= rcdev->nr_resets || !info->resets[id].off) {
560560
dev_err(rcdev->dev, "Invalid reset index %u\n", id);
561561
return -EINVAL;
562562
}
@@ -571,7 +571,7 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
571571
priv->rcdev.dev = priv->dev;
572572
priv->rcdev.of_reset_n_cells = 1;
573573
priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
574-
priv->rcdev.nr_resets = priv->num_mod_clks;
574+
priv->rcdev.nr_resets = priv->num_resets;
575575

576576
return devm_reset_controller_register(priv->dev, &priv->rcdev);
577577
}
@@ -594,42 +594,49 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device
594594
{
595595
struct device_node *np = dev->of_node;
596596
struct of_phandle_args clkspec;
597+
bool once = true;
597598
struct clk *clk;
598599
int error;
599600
int i = 0;
600601

601602
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
602603
&clkspec)) {
603-
if (rzg2l_cpg_is_pm_clk(&clkspec))
604-
goto found;
605-
606-
of_node_put(clkspec.np);
604+
if (rzg2l_cpg_is_pm_clk(&clkspec)) {
605+
if (once) {
606+
once = false;
607+
error = pm_clk_create(dev);
608+
if (error) {
609+
of_node_put(clkspec.np);
610+
goto err;
611+
}
612+
}
613+
clk = of_clk_get_from_provider(&clkspec);
614+
of_node_put(clkspec.np);
615+
if (IS_ERR(clk)) {
616+
error = PTR_ERR(clk);
617+
goto fail_destroy;
618+
}
619+
620+
error = pm_clk_add_clk(dev, clk);
621+
if (error) {
622+
dev_err(dev, "pm_clk_add_clk failed %d\n",
623+
error);
624+
goto fail_put;
625+
}
626+
} else {
627+
of_node_put(clkspec.np);
628+
}
607629
i++;
608630
}
609631

610632
return 0;
611633

612-
found:
613-
clk = of_clk_get_from_provider(&clkspec);
614-
of_node_put(clkspec.np);
615-
616-
if (IS_ERR(clk))
617-
return PTR_ERR(clk);
618-
619-
error = pm_clk_create(dev);
620-
if (error)
621-
goto fail_put;
622-
623-
error = pm_clk_add_clk(dev, clk);
624-
if (error)
625-
goto fail_destroy;
626-
627-
return 0;
634+
fail_put:
635+
clk_put(clk);
628636

629637
fail_destroy:
630638
pm_clk_destroy(dev);
631-
fail_put:
632-
clk_put(clk);
639+
err:
633640
return error;
634641
}
635642

@@ -692,6 +699,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
692699
priv->clks = clks;
693700
priv->num_core_clks = info->num_total_core_clks;
694701
priv->num_mod_clks = info->num_hw_mod_clks;
702+
priv->num_resets = info->num_resets;
695703
priv->last_dt_core_clk = info->last_dt_core_clk;
696704

697705
for (i = 0; i < nclks; i++)

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