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AngeloGioacchino Del Regnobebarino
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clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe()
Since the common simple probe function for MediaTek clock drivers can now register the MFG MUX notifier, it's possible to migrate MT8192's topckgen to that, allowing for some code size reduction. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20230120092053.182923-20-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Lines changed: 17 additions & 68 deletions

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drivers/clk/mediatek/clk-mt8192.c

Lines changed: 17 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -1064,71 +1064,6 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
10641064
return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
10651065
}
10661066

1067-
static int clk_mt8192_top_probe(struct platform_device *pdev)
1068-
{
1069-
struct device_node *node = pdev->dev.of_node;
1070-
struct clk_hw_onecell_data *top_clk_data;
1071-
int r;
1072-
void __iomem *base;
1073-
1074-
base = devm_platform_ioremap_resource(pdev, 0);
1075-
if (IS_ERR(base))
1076-
return PTR_ERR(base);
1077-
1078-
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1079-
if (!top_clk_data)
1080-
return -ENOMEM;
1081-
1082-
r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1083-
if (r)
1084-
return r;
1085-
1086-
r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1087-
if (r)
1088-
goto unregister_fixed_clks;
1089-
1090-
r = mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes,
1091-
ARRAY_SIZE(top_mtk_muxes), node,
1092-
&mt8192_clk_lock, top_clk_data);
1093-
if (r)
1094-
goto unregister_factors;
1095-
1096-
r = mtk_clk_register_composites(&pdev->dev, top_muxes,
1097-
ARRAY_SIZE(top_muxes), base,
1098-
&mt8192_clk_lock, top_clk_data);
1099-
if (r)
1100-
goto unregister_muxes;
1101-
1102-
r = mtk_clk_register_gates(&pdev->dev, node, top_clks,
1103-
ARRAY_SIZE(top_clks), top_clk_data);
1104-
if (r)
1105-
goto unregister_top_composites;
1106-
1107-
r = clk_mt8192_reg_mfg_mux_notifier(&pdev->dev,
1108-
top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk);
1109-
if (r)
1110-
goto unregister_gates;
1111-
1112-
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1113-
if (r)
1114-
goto unregister_gates;
1115-
1116-
return 0;
1117-
1118-
unregister_gates:
1119-
mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1120-
unregister_top_composites:
1121-
mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data);
1122-
unregister_muxes:
1123-
mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1124-
unregister_factors:
1125-
mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1126-
unregister_fixed_clks:
1127-
mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1128-
top_clk_data);
1129-
return r;
1130-
}
1131-
11321067
static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
11331068
{
11341069
struct clk_hw_onecell_data *clk_data;
@@ -1162,9 +1097,6 @@ static const struct of_device_id of_match_clk_mt8192[] = {
11621097
{
11631098
.compatible = "mediatek,mt8192-apmixedsys",
11641099
.data = clk_mt8192_apmixed_probe,
1165-
}, {
1166-
.compatible = "mediatek,mt8192-topckgen",
1167-
.data = clk_mt8192_top_probe,
11681100
}, {
11691101
/* sentinel */
11701102
}
@@ -1197,9 +1129,26 @@ static const struct mtk_clk_desc peri_desc = {
11971129
.num_clks = ARRAY_SIZE(peri_clks),
11981130
};
11991131

1132+
static const struct mtk_clk_desc topck_desc = {
1133+
.fixed_clks = top_fixed_clks,
1134+
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
1135+
.factor_clks = top_divs,
1136+
.num_factor_clks = ARRAY_SIZE(top_divs),
1137+
.mux_clks = top_mtk_muxes,
1138+
.num_mux_clks = ARRAY_SIZE(top_mtk_muxes),
1139+
.composite_clks = top_muxes,
1140+
.num_composite_clks = ARRAY_SIZE(top_muxes),
1141+
.clks = top_clks,
1142+
.num_clks = ARRAY_SIZE(top_clks),
1143+
.clk_lock = &mt8192_clk_lock,
1144+
.clk_notifier_func = clk_mt8192_reg_mfg_mux_notifier,
1145+
.mfg_clk_idx = CLK_TOP_MFG_PLL_SEL,
1146+
};
1147+
12001148
static const struct of_device_id of_match_clk_mt8192_simple[] = {
12011149
{ .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc },
12021150
{ .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc },
1151+
{ .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc },
12031152
{ /* sentinel */ }
12041153
};
12051154

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