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bebarinobebarino
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Merge tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet: - pll driver fixup - meson8b clock controller dt support clean up - remove mipi clk from the axg clock controller * tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson: clk: meson: axg: Remove MIPI enable clock gate clk: meson-axg: remove CLKID_MIPI_ENABLE dt-bindings: clock: meson8b: remove non-existing clock macros clk: meson: meson8b: remove compatibility code for old .dtbs clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() clk: meson: clk-pll: make "ret" a signed integer clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL
2 parents 5c8fe58 + 3103583 commit e3272b0

6 files changed

Lines changed: 11 additions & 51 deletions

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‎drivers/clk/meson/axg.c‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1879,7 +1879,6 @@ static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
18791879
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
18801880
static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
18811881
static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1882-
static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
18831882

18841883
/* Always On (AO) domain gates */
18851884

@@ -1974,7 +1973,6 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
19741973
[CLKID_PCIE_REF] = &axg_pcie_ref.hw,
19751974
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
19761975
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1977-
[CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
19781976
[CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
19791977
[CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
19801978
[CLKID_GEN_CLK] = &axg_gen_clk.hw,
@@ -2115,7 +2113,6 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
21152113
&axg_pcie_ref,
21162114
&axg_pcie_cml_en0,
21172115
&axg_pcie_cml_en1,
2118-
&axg_mipi_enable,
21192116
&axg_gen_clk_sel,
21202117
&axg_gen_clk_div,
21212118
&axg_gen_clk,

‎drivers/clk/meson/axg.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@
1616
* Register offsets from the data sheet must be multiplied by 4 before
1717
* adding them to the base address to get the right value.
1818
*/
19-
#define HHI_MIPI_CNTL0 0x00
2019
#define HHI_GP0_PLL_CNTL 0x40
2120
#define HHI_GP0_PLL_CNTL2 0x44
2221
#define HHI_GP0_PLL_CNTL3 0x48

‎drivers/clk/meson/clk-pll.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -365,13 +365,14 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
365365
{
366366
struct clk_regmap *clk = to_clk_regmap(hw);
367367
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
368-
unsigned int enabled, m, n, frac = 0, ret;
368+
unsigned int enabled, m, n, frac = 0;
369369
unsigned long old_rate;
370+
int ret;
370371

371372
if (parent_rate == 0 || rate == 0)
372373
return -EINVAL;
373374

374-
old_rate = rate;
375+
old_rate = clk_hw_get_rate(hw);
375376

376377
ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
377378
if (ret)
@@ -393,7 +394,8 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
393394
if (!enabled)
394395
return 0;
395396

396-
if (meson_clk_pll_enable(hw)) {
397+
ret = meson_clk_pll_enable(hw);
398+
if (ret) {
397399
pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
398400
__func__, old_rate);
399401
/*
@@ -405,7 +407,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
405407
meson_clk_pll_set_rate(hw, old_rate, parent_rate);
406408
}
407409

408-
return 0;
410+
return ret;
409411
}
410412

411413
/*

‎drivers/clk/meson/meson8b.c‎

Lines changed: 5 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -52,15 +52,6 @@ static const struct pll_params_table sys_pll_params_table[] = {
5252
{ /* sentinel */ },
5353
};
5454

55-
static struct clk_fixed_rate meson8b_xtal = {
56-
.fixed_rate = 24000000,
57-
.hw.init = &(struct clk_init_data){
58-
.name = "xtal",
59-
.num_parents = 0,
60-
.ops = &clk_fixed_rate_ops,
61-
},
62-
};
63-
6455
static struct clk_regmap meson8b_fixed_pll_dco = {
6556
.data = &(struct meson_clk_pll_data){
6657
.en = {
@@ -2715,7 +2706,6 @@ static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
27152706

27162707
static struct clk_hw_onecell_data meson8_hw_onecell_data = {
27172708
.hws = {
2718-
[CLKID_XTAL] = &meson8b_xtal.hw,
27192709
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
27202710
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
27212711
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
@@ -2922,7 +2912,6 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
29222912

29232913
static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
29242914
.hws = {
2925-
[CLKID_XTAL] = &meson8b_xtal.hw,
29262915
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
29272916
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
29282917
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
@@ -3140,7 +3129,6 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
31403129

31413130
static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
31423131
.hws = {
3143-
[CLKID_XTAL] = &meson8b_xtal.hw,
31443132
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
31453133
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
31463134
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
@@ -3725,36 +3713,19 @@ static struct meson8b_nb_data meson8b_cpu_nb_data = {
37253713
.nb.notifier_call = meson8b_cpu_clk_notifier_cb,
37263714
};
37273715

3728-
static const struct regmap_config clkc_regmap_config = {
3729-
.reg_bits = 32,
3730-
.val_bits = 32,
3731-
.reg_stride = 4,
3732-
};
3733-
37343716
static void __init meson8b_clkc_init_common(struct device_node *np,
37353717
struct clk_hw_onecell_data *clk_hw_onecell_data)
37363718
{
37373719
struct meson8b_clk_reset *rstc;
37383720
const char *notifier_clk_name;
37393721
struct clk *notifier_clk;
3740-
void __iomem *clk_base;
37413722
struct regmap *map;
37423723
int i, ret;
37433724

37443725
map = syscon_node_to_regmap(of_get_parent(np));
37453726
if (IS_ERR(map)) {
3746-
pr_info("failed to get HHI regmap - Trying obsolete regs\n");
3747-
3748-
/* Generic clocks, PLLs and some of the reset-bits */
3749-
clk_base = of_iomap(np, 1);
3750-
if (!clk_base) {
3751-
pr_err("%s: Unable to map clk base\n", __func__);
3752-
return;
3753-
}
3754-
3755-
map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
3756-
if (IS_ERR(map))
3757-
return;
3727+
pr_err("failed to get HHI regmap - Trying obsolete regs\n");
3728+
return;
37583729
}
37593730

37603731
rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
@@ -3778,16 +3749,10 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
37783749
meson8b_clk_regmaps[i]->map = map;
37793750

37803751
/*
3781-
* always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the
3782-
* XTAL clock as input.
3752+
* register all clks and start with the first used ID (which is
3753+
* CLKID_PLL_FIXED)
37833754
*/
3784-
if (!IS_ERR(of_clk_get_by_name(np, "xtal")))
3785-
i = CLKID_PLL_FIXED;
3786-
else
3787-
i = CLKID_XTAL;
3788-
3789-
/* register all clks */
3790-
for (; i < CLK_NR_CLKS; i++) {
3755+
for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) {
37913756
/* array might be sparse */
37923757
if (!clk_hw_onecell_data->hws[i])
37933758
continue;

‎include/dt-bindings/clock/axg-clkc.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,6 @@
7070
#define CLKID_HIFI_PLL 69
7171
#define CLKID_PCIE_CML_EN0 79
7272
#define CLKID_PCIE_CML_EN1 80
73-
#define CLKID_MIPI_ENABLE 81
7473
#define CLKID_GEN_CLK 84
7574
#define CLKID_VPU_0_SEL 92
7675
#define CLKID_VPU_0 93

‎include/dt-bindings/clock/meson8b-clkc.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,6 @@
66
#ifndef __MESON8B_CLKC_H
77
#define __MESON8B_CLKC_H
88

9-
#define CLKID_UNUSED 0
10-
#define CLKID_XTAL 1
119
#define CLKID_PLL_FIXED 2
1210
#define CLKID_PLL_VID 3
1311
#define CLKID_PLL_SYS 4

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