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lynxeye-devShawn Guo
lynxeye-dev
authored and
Shawn Guo
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soc: imx: add i.MX8MP HDMI blk-ctrl
This adds driver support for the HDMI blk-ctrl found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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‎drivers/soc/imx/imx8mp-blk-ctrl.c‎

Lines changed: 193 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -174,6 +174,196 @@ static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
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.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
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};
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#define HDMI_RTX_RESET_CTL0 0x20
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#define HDMI_RTX_CLK_CTL0 0x40
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#define HDMI_RTX_CLK_CTL1 0x50
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#define HDMI_RTX_CLK_CTL2 0x60
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#define HDMI_RTX_CLK_CTL3 0x70
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#define HDMI_RTX_CLK_CTL4 0x80
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#define HDMI_TX_CONTROL0 0x200
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static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
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struct imx8mp_blk_ctrl_domain *domain)
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{
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switch (domain->id) {
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case IMX8MP_HDMIBLK_PD_IRQSTEER:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
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break;
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case IMX8MP_HDMIBLK_PD_LCDIF:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
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BIT(7) | BIT(16) | BIT(17) | BIT(18) |
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BIT(19) | BIT(20));
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
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BIT(4) | BIT(5) | BIT(6));
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break;
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case IMX8MP_HDMIBLK_PD_PAI:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
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break;
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case IMX8MP_HDMIBLK_PD_PVI:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
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break;
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case IMX8MP_HDMIBLK_PD_TRNG:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
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break;
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case IMX8MP_HDMIBLK_PD_HDMI_TX:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
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BIT(2) | BIT(4) | BIT(5));
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
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BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
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BIT(18) | BIT(19) | BIT(20) | BIT(21));
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
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BIT(7) | BIT(10) | BIT(11));
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regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
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break;
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case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
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regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
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break;
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default:
229+
break;
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}
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}
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static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
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struct imx8mp_blk_ctrl_domain *domain)
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{
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switch (domain->id) {
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case IMX8MP_HDMIBLK_PD_IRQSTEER:
238+
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
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regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
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break;
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case IMX8MP_HDMIBLK_PD_LCDIF:
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regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
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BIT(4) | BIT(5) | BIT(6));
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regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
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regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
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BIT(7) | BIT(16) | BIT(17) | BIT(18) |
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BIT(19) | BIT(20));
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break;
249+
case IMX8MP_HDMIBLK_PD_PAI:
250+
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
251+
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
252+
break;
253+
case IMX8MP_HDMIBLK_PD_PVI:
254+
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
255+
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
256+
break;
257+
case IMX8MP_HDMIBLK_PD_TRNG:
258+
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
259+
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
260+
break;
261+
case IMX8MP_HDMIBLK_PD_HDMI_TX:
262+
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
263+
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
264+
BIT(7) | BIT(10) | BIT(11));
265+
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
266+
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
267+
BIT(18) | BIT(19) | BIT(20) | BIT(21));
268+
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
269+
BIT(2) | BIT(4) | BIT(5));
270+
break;
271+
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
272+
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
273+
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
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regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
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break;
276+
default:
277+
break;
278+
}
279+
}
280+
281+
static int imx8mp_hdmi_power_notifier(struct notifier_block *nb,
282+
unsigned long action, void *data)
283+
{
284+
struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
285+
power_nb);
286+
287+
if (action != GENPD_NOTIFY_ON)
288+
return NOTIFY_OK;
289+
290+
/*
291+
* Contrary to other blk-ctrls the reset and clock don't clear when the
292+
* power domain is powered down. To ensure the proper reset pulsing,
293+
* first clear them all to asserted state, then enable the bus clocks
294+
* and then release the ADB reset.
295+
*/
296+
regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0);
297+
regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
298+
regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
299+
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
300+
BIT(0) | BIT(1) | BIT(10));
301+
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
302+
303+
/*
304+
* On power up we have no software backchannel to the GPC to
305+
* wait for the ADB handshake to happen, so we just delay for a
306+
* bit. On power down the GPC driver waits for the handshake.
307+
*/
308+
udelay(5);
309+
310+
return NOTIFY_OK;
311+
}
312+
313+
static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = {
314+
[IMX8MP_HDMIBLK_PD_IRQSTEER] = {
315+
.name = "hdmiblk-irqsteer",
316+
.clk_names = (const char *[]){ "apb" },
317+
.num_clks = 1,
318+
.gpc_name = "irqsteer",
319+
},
320+
[IMX8MP_HDMIBLK_PD_LCDIF] = {
321+
.name = "hdmiblk-lcdif",
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.clk_names = (const char *[]){ "axi", "apb" },
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.num_clks = 2,
324+
.gpc_name = "lcdif",
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},
326+
[IMX8MP_HDMIBLK_PD_PAI] = {
327+
.name = "hdmiblk-pai",
328+
.clk_names = (const char *[]){ "apb" },
329+
.num_clks = 1,
330+
.gpc_name = "pai",
331+
},
332+
[IMX8MP_HDMIBLK_PD_PVI] = {
333+
.name = "hdmiblk-pvi",
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.clk_names = (const char *[]){ "apb" },
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.num_clks = 1,
336+
.gpc_name = "pvi",
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},
338+
[IMX8MP_HDMIBLK_PD_TRNG] = {
339+
.name = "hdmiblk-trng",
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.clk_names = (const char *[]){ "apb" },
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.num_clks = 1,
342+
.gpc_name = "trng",
343+
},
344+
[IMX8MP_HDMIBLK_PD_HDMI_TX] = {
345+
.name = "hdmiblk-hdmi-tx",
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.clk_names = (const char *[]){ "apb", "ref_266m" },
347+
.num_clks = 2,
348+
.gpc_name = "hdmi-tx",
349+
},
350+
[IMX8MP_HDMIBLK_PD_HDMI_TX_PHY] = {
351+
.name = "hdmiblk-hdmi-tx-phy",
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.clk_names = (const char *[]){ "apb", "ref_24m" },
353+
.num_clks = 2,
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.gpc_name = "hdmi-tx-phy",
355+
},
356+
};
357+
358+
static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {
359+
.max_reg = 0x23c,
360+
.power_on = imx8mp_hdmi_blk_ctrl_power_on,
361+
.power_off = imx8mp_hdmi_blk_ctrl_power_off,
362+
.power_notifier_fn = imx8mp_hdmi_power_notifier,
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.domains = imx8mp_hdmi_domain_data,
364+
.num_domains = ARRAY_SIZE(imx8mp_hdmi_domain_data),
365+
};
366+
177367
static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
178368
{
179369
struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
@@ -485,6 +675,9 @@ static const struct of_device_id imx8mp_blk_ctrl_of_match[] = {
485675
{
486676
.compatible = "fsl,imx8mp-hsio-blk-ctrl",
487677
.data = &imx8mp_hsio_blk_ctl_dev_data,
678+
}, {
679+
.compatible = "fsl,imx8mp-hdmi-blk-ctrl",
680+
.data = &imx8mp_hdmi_blk_ctl_dev_data,
488681
}, {
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/* Sentinel */
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}

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