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torvaldstorvalds
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Merge tag 'drm-fixes-2022-10-28' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Regularly scheduled fixes for drm, live from a Red Hat office for the first time in a while. The core has two fixes, one for scheduler leak and one for aperture uninit read. Otherwise a single bridge fix, and msm, amdgpu/kfd and i915 have a set of fixes each. sched: - Stop leaking fences when killing a sched entity. aperture: - Avoid uninitialized read in aperture_remove_conflicting_pci_device() bridge: - Fix HPD on bridge/ps8640. msm: - Fix shrinker deadlock - Fix crash during suspend after unbind - Fix IRQ lifetime issues - Fix potential memory corruption with too many bridges - Fix memory corruption on GPU state capture amdgpu: - Stable pstate fix - SMU 13.x updates - SR-IOV fixes - PCI AER fix - GC 11.x fixes - Display fixes - Expose IMU firmware version for debugging - Plane modifier fix - S0i3 fix amdkfd: - Fix possible memory leak - Fix GC 10.x cache info reporting i915: - Extend Wa_1607297627 to Alderlake-P - Keep PCI autosuspend control 'on' by default on all dGPU - Reset frl trained flag before restarting FRL training" * tag 'drm-fixes-2022-10-28' of git://anongit.freedesktop.org/drm/drm: (39 commits) fbdev/core: Avoid uninitialized read in aperture_remove_conflicting_pci_device() drm/amdgpu: disallow gfxoff until GC IP blocks complete s2idle resume drm/scheduler: fix fence ref counting drm/amd/display: Revert logic for plane modifiers drm/amdkfd: correct the cache info for gfx1036 drm/amdkfd: update gfx1037 Lx cache setting drm/amdgpu: skip mes self test for gc 11.0.3 in recover drm/amd: Add IMU fw version to fw version queries drm/amd/display: Don't return false if no stream drm/amd/display: Remove wrong pipe control lock drm/amd/pm: allow gfxoff on gc_11_0_3 drm/amdkfd: Fix memory leak in kfd_mem_dmamap_userptr() drm/amdgpu: Remove ATC L2 access for MMHUB 2.1.x drm/i915/dp: Reset frl trained flag before restarting FRL training drm/i915/dgfx: Keep PCI autosuspend control 'on' by default on all dGPU drm/i915: Extend Wa_1607297627 to Alderlake-P drm/amdgpu: Adjust MES polling timeout for sriov drm/amd/pm: update driver-if header for smu_v13_0_10 drm/amdgpu: fix pstate setting issue drm/bridge: ps8640: Add back the 50 ms mystery delay after HPD ...
2 parents 05c31d2 + b219640 commit e3493d6

41 files changed

Lines changed: 421 additions & 161 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -510,13 +510,13 @@ kfd_mem_dmamap_userptr(struct kgd_mem *mem,
510510
struct ttm_tt *ttm = bo->tbo.ttm;
511511
int ret;
512512

513+
if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
514+
return -EINVAL;
515+
513516
ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
514517
if (unlikely(!ttm->sg))
515518
return -ENOMEM;
516519

517-
if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
518-
return -EINVAL;
519-
520520
/* Same sequence as in amdgpu_ttm_tt_pin_userptr */
521521
ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
522522
ttm->num_pages, 0,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,10 @@ static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority,
326326
if (r)
327327
return r;
328328

329-
ctx->stable_pstate = current_stable_pstate;
329+
if (mgr->adev->pm.stable_pstate_ctx)
330+
ctx->stable_pstate = mgr->adev->pm.stable_pstate_ctx->stable_pstate;
331+
else
332+
ctx->stable_pstate = current_stable_pstate;
330333

331334
return 0;
332335
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3210,6 +3210,15 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
32103210
return r;
32113211
}
32123212
adev->ip_blocks[i].status.hw = true;
3213+
3214+
if (adev->in_s0ix && adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3215+
/* disable gfxoff for IP resume. The gfxoff will be re-enabled in
3216+
* amdgpu_device_resume() after IP resume.
3217+
*/
3218+
amdgpu_gfx_off_ctrl(adev, false);
3219+
DRM_DEBUG("will disable gfxoff for re-initializing other blocks\n");
3220+
}
3221+
32133222
}
32143223

32153224
return 0;
@@ -4185,6 +4194,13 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
41854194
/* Make sure IB tests flushed */
41864195
flush_delayed_work(&adev->delayed_init_work);
41874196

4197+
if (adev->in_s0ix) {
4198+
/* re-enable gfxoff after IP resume. This re-enables gfxoff after
4199+
* it was disabled for IP resume in amdgpu_device_ip_resume_phase2().
4200+
*/
4201+
amdgpu_gfx_off_ctrl(adev, true);
4202+
DRM_DEBUG("will enable gfxoff for the mission mode\n");
4203+
}
41884204
if (fbcon)
41894205
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
41904206

@@ -5381,7 +5397,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
53815397
drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
53825398
}
53835399

5384-
if (adev->enable_mes)
5400+
if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))
53855401
amdgpu_mes_self_test(tmp_adev);
53865402

53875403
if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -344,6 +344,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
344344
fw_info->ver = adev->mes.ucode_fw_version[1];
345345
fw_info->feature = 0;
346346
break;
347+
case AMDGPU_INFO_FW_IMU:
348+
fw_info->ver = adev->gfx.imu_fw_version;
349+
fw_info->feature = 0;
350+
break;
347351
default:
348352
return -EINVAL;
349353
}
@@ -1520,6 +1524,15 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
15201524
fw_info.feature, fw_info.ver);
15211525
}
15221526

1527+
/* IMU */
1528+
query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1529+
query_fw.index = 0;
1530+
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1531+
if (ret)
1532+
return ret;
1533+
seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1534+
fw_info.feature, fw_info.ver);
1535+
15231536
/* PSP SOS */
15241537
query_fw.fw_type = AMDGPU_INFO_FW_SOS;
15251538
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -698,6 +698,7 @@ FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
698698
FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
699699
FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
700700
FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
701+
FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
701702
FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
702703
FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
703704
FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
@@ -719,7 +720,8 @@ static struct attribute *fw_attrs[] = {
719720
&dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
720721
&dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
721722
&dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
722-
&dev_attr_dmcu_fw_version.attr, NULL
723+
&dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr,
724+
NULL
723725
};
724726

725727
static const struct attribute_group fw_attr_group = {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -547,6 +547,7 @@ static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
547547
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
548548
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version);
549549
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version);
550+
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_IMU, adev->gfx.imu_fw_version);
550551
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version);
551552
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,
552553
adev->psp.asd_context.bin_desc.fw_version);

‎drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ enum amd_sriov_ucode_engine_id {
7070
AMD_SRIOV_UCODE_ID_RLC_SRLS,
7171
AMD_SRIOV_UCODE_ID_MEC,
7272
AMD_SRIOV_UCODE_ID_MEC2,
73+
AMD_SRIOV_UCODE_ID_IMU,
7374
AMD_SRIOV_UCODE_ID_SOS,
7475
AMD_SRIOV_UCODE_ID_ASD,
7576
AMD_SRIOV_UCODE_ID_TA_RAS,

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5051,6 +5051,7 @@ static int gfx_v11_0_set_powergating_state(void *handle,
50515051
switch (adev->ip_versions[GC_HWIP][0]) {
50525052
case IP_VERSION(11, 0, 0):
50535053
case IP_VERSION(11, 0, 2):
5054+
case IP_VERSION(11, 0, 3):
50545055
amdgpu_gfx_off_ctrl(adev, enable);
50555056
break;
50565057
case IP_VERSION(11, 0, 1):

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,14 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
9898
struct amdgpu_device *adev = mes->adev;
9999
struct amdgpu_ring *ring = &mes->ring;
100100
unsigned long flags;
101+
signed long timeout = adev->usec_timeout;
101102

103+
if (amdgpu_emu_mode) {
104+
timeout *= 100;
105+
} else if (amdgpu_sriov_vf(adev)) {
106+
/* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
107+
timeout = 15 * 600 * 1000;
108+
}
102109
BUG_ON(size % 4 != 0);
103110

104111
spin_lock_irqsave(&mes->ring_lock, flags);
@@ -118,7 +125,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
118125
DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
119126

120127
r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
121-
adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1));
128+
timeout);
122129
if (r < 1) {
123130
DRM_ERROR("MES failed to response msg=%d\n",
124131
x_pkt->header.opcode);

‎drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c‎

Lines changed: 8 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,6 @@
3232
#include "gc/gc_10_1_0_offset.h"
3333
#include "soc15_common.h"
3434

35-
#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d
36-
#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX 0
3735
#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
3836
#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
3937

@@ -574,7 +572,6 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
574572
case IP_VERSION(2, 1, 0):
575573
case IP_VERSION(2, 1, 1):
576574
case IP_VERSION(2, 1, 2):
577-
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
578575
def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
579576
break;
580577
default:
@@ -608,8 +605,6 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
608605
case IP_VERSION(2, 1, 0):
609606
case IP_VERSION(2, 1, 1):
610607
case IP_VERSION(2, 1, 2):
611-
if (def != data)
612-
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
613608
if (def1 != data1)
614609
WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
615610
break;
@@ -634,8 +629,8 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
634629
case IP_VERSION(2, 1, 0):
635630
case IP_VERSION(2, 1, 1):
636631
case IP_VERSION(2, 1, 2):
637-
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
638-
break;
632+
/* There is no ATCL2 in MMHUB for 2.1.x */
633+
return;
639634
default:
640635
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
641636
break;
@@ -646,18 +641,8 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
646641
else
647642
data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
648643

649-
if (def != data) {
650-
switch (adev->ip_versions[MMHUB_HWIP][0]) {
651-
case IP_VERSION(2, 1, 0):
652-
case IP_VERSION(2, 1, 1):
653-
case IP_VERSION(2, 1, 2):
654-
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
655-
break;
656-
default:
657-
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
658-
break;
659-
}
660-
}
644+
if (def != data)
645+
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
661646
}
662647

663648
static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
@@ -695,7 +680,10 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
695680
case IP_VERSION(2, 1, 0):
696681
case IP_VERSION(2, 1, 1):
697682
case IP_VERSION(2, 1, 2):
698-
data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
683+
/* There is no ATCL2 in MMHUB for 2.1.x. Keep the status
684+
* based on DAGB
685+
*/
686+
data = MM_ATC_L2_MISC_CG__ENABLE_MASK;
699687
data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
700688
break;
701689
default:

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