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Gary YangPeter Chen
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arm64: dts: cix: Add OrangePi 6 Plus board support
OrangePi 6 Plus adopts CIX CD8180/CD8160 SoC, built-in 12-core 64-bit processor + NPU processor,integrated graphics processor, equipped with 16GB/32GB/64GB LPDDR5, and provides two M.2 KEY-M interfaces 2280 for NVMe SSD,as well as SPI FLASH and TF slots to meet the needs of fast read/write and high-capacity storage Signed-off-by: Gary Yang <gary.yang@cixtech.com> Link: https://lore.kernel.org/r/20260110093406.2700505-3-gary.yang@cixtech.com Signed-off-by: Peter Chen <peter.chen@cixtech.com>
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arch/arm64/boot/dts/cix/Makefile

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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb
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dtb-$(CONFIG_ARCH_CIX) += sky1-xcp.dtb
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright 2025 Cix Technology Group Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "sky1.dtsi"
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#include "sky1-pinfunc.h"
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/ {
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model = "Xunlong,OrangePi 6 Plus";
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compatible = "xunlong,orangepi-6-plus", "cix,sky1";
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aliases {
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serial2 = &uart2;
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};
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chosen {
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stdout-path = &uart2;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x28000000>;
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linux,cma-default;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hog-cfg {
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pins {
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pinmux = <CIX_PAD_GPIO144_FUNC_GPIO144>,
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<CIX_PAD_GPIO145_FUNC_GPIO145>,
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<CIX_PAD_GPIO146_FUNC_GPIO146>,
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<CIX_PAD_GPIO147_FUNC_GPIO147>;
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bias-pull-down;
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drive-strength = <8>;
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};
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};
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};
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&iomuxc_s5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_s5>;
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pinctrl_hog_s5: hog-s5-cfg {
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pins {
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pinmux = <CIX_PAD_GPIO014_FUNC_GPIO014>;
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bias-pull-up;
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drive-strength = <8>;
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};
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};
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};
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&pcie_x8_rc {
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status = "okay";
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};
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&pcie_x2_rc {
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status = "okay";
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};
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&pcie_x1_1_rc {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};

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