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konradybcioGeorgi Djakov
konradybcio
authored and
Georgi Djakov
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interconnect: qcom: sc7180: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-11-c03aaeffc769@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Lines changed: 231 additions & 24 deletions

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‎drivers/interconnect/qcom/sc7180.c‎

Lines changed: 231 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1236,30 +1236,237 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
12361236
.buswidth = 8,
12371237
};
12381238

1239-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1240-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1241-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1242-
DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
1243-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1244-
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
1245-
DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
1246-
DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
1247-
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
1248-
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
1249-
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
1250-
DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0);
1251-
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
1252-
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
1253-
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
1254-
DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2);
1255-
DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc);
1256-
DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
1257-
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
1258-
DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
1259-
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
1260-
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
1261-
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc);
1262-
DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc);
1239+
static struct qcom_icc_bcm bcm_acv = {
1240+
.name = "ACV",
1241+
.keepalive = false,
1242+
.num_nodes = 1,
1243+
.nodes = { &ebi },
1244+
};
1245+
1246+
static struct qcom_icc_bcm bcm_mc0 = {
1247+
.name = "MC0",
1248+
.keepalive = true,
1249+
.num_nodes = 1,
1250+
.nodes = { &ebi },
1251+
};
1252+
1253+
static struct qcom_icc_bcm bcm_sh0 = {
1254+
.name = "SH0",
1255+
.keepalive = true,
1256+
.num_nodes = 1,
1257+
.nodes = { &qns_llcc },
1258+
};
1259+
1260+
static struct qcom_icc_bcm bcm_mm0 = {
1261+
.name = "MM0",
1262+
.keepalive = false,
1263+
.num_nodes = 1,
1264+
.nodes = { &qns_mem_noc_hf },
1265+
};
1266+
1267+
static struct qcom_icc_bcm bcm_ce0 = {
1268+
.name = "CE0",
1269+
.keepalive = false,
1270+
.num_nodes = 1,
1271+
.nodes = { &qxm_crypto },
1272+
};
1273+
1274+
static struct qcom_icc_bcm bcm_cn0 = {
1275+
.name = "CN0",
1276+
.keepalive = true,
1277+
.num_nodes = 48,
1278+
.nodes = { &qnm_snoc,
1279+
&xm_qdss_dap,
1280+
&qhs_a1_noc_cfg,
1281+
&qhs_a2_noc_cfg,
1282+
&qhs_ahb2phy0,
1283+
&qhs_aop,
1284+
&qhs_aoss,
1285+
&qhs_boot_rom,
1286+
&qhs_camera_cfg,
1287+
&qhs_camera_nrt_throttle_cfg,
1288+
&qhs_camera_rt_throttle_cfg,
1289+
&qhs_clk_ctl,
1290+
&qhs_cpr_cx,
1291+
&qhs_cpr_mx,
1292+
&qhs_crypto0_cfg,
1293+
&qhs_dcc_cfg,
1294+
&qhs_ddrss_cfg,
1295+
&qhs_display_cfg,
1296+
&qhs_display_rt_throttle_cfg,
1297+
&qhs_display_throttle_cfg,
1298+
&qhs_glm,
1299+
&qhs_gpuss_cfg,
1300+
&qhs_imem_cfg,
1301+
&qhs_ipa,
1302+
&qhs_mnoc_cfg,
1303+
&qhs_mss_cfg,
1304+
&qhs_npu_cfg,
1305+
&qhs_npu_dma_throttle_cfg,
1306+
&qhs_npu_dsp_throttle_cfg,
1307+
&qhs_pimem_cfg,
1308+
&qhs_prng,
1309+
&qhs_qdss_cfg,
1310+
&qhs_qm_cfg,
1311+
&qhs_qm_mpu_cfg,
1312+
&qhs_qup0,
1313+
&qhs_qup1,
1314+
&qhs_security,
1315+
&qhs_snoc_cfg,
1316+
&qhs_tcsr,
1317+
&qhs_tlmm_1,
1318+
&qhs_tlmm_2,
1319+
&qhs_tlmm_3,
1320+
&qhs_ufs_mem_cfg,
1321+
&qhs_usb3,
1322+
&qhs_venus_cfg,
1323+
&qhs_venus_throttle_cfg,
1324+
&qhs_vsense_ctrl_cfg,
1325+
&srvc_cnoc
1326+
},
1327+
};
1328+
1329+
static struct qcom_icc_bcm bcm_mm1 = {
1330+
.name = "MM1",
1331+
.keepalive = false,
1332+
.num_nodes = 8,
1333+
.nodes = { &qxm_camnoc_hf0_uncomp,
1334+
&qxm_camnoc_hf1_uncomp,
1335+
&qxm_camnoc_sf_uncomp,
1336+
&qhm_mnoc_cfg,
1337+
&qxm_mdp0,
1338+
&qxm_rot,
1339+
&qxm_venus0,
1340+
&qxm_venus_arm9
1341+
},
1342+
};
1343+
1344+
static struct qcom_icc_bcm bcm_sh2 = {
1345+
.name = "SH2",
1346+
.keepalive = false,
1347+
.num_nodes = 1,
1348+
.nodes = { &acm_sys_tcu },
1349+
};
1350+
1351+
static struct qcom_icc_bcm bcm_mm2 = {
1352+
.name = "MM2",
1353+
.keepalive = false,
1354+
.num_nodes = 1,
1355+
.nodes = { &qns_mem_noc_sf },
1356+
};
1357+
1358+
static struct qcom_icc_bcm bcm_qup0 = {
1359+
.name = "QUP0",
1360+
.keepalive = false,
1361+
.num_nodes = 2,
1362+
.nodes = { &qup_core_master_1, &qup_core_master_2 },
1363+
};
1364+
1365+
static struct qcom_icc_bcm bcm_sh3 = {
1366+
.name = "SH3",
1367+
.keepalive = false,
1368+
.num_nodes = 1,
1369+
.nodes = { &qnm_cmpnoc },
1370+
};
1371+
1372+
static struct qcom_icc_bcm bcm_sh4 = {
1373+
.name = "SH4",
1374+
.keepalive = false,
1375+
.num_nodes = 1,
1376+
.nodes = { &acm_apps0 },
1377+
};
1378+
1379+
static struct qcom_icc_bcm bcm_sn0 = {
1380+
.name = "SN0",
1381+
.keepalive = true,
1382+
.num_nodes = 1,
1383+
.nodes = { &qns_gemnoc_sf },
1384+
};
1385+
1386+
static struct qcom_icc_bcm bcm_co0 = {
1387+
.name = "CO0",
1388+
.keepalive = false,
1389+
.num_nodes = 1,
1390+
.nodes = { &qns_cdsp_gemnoc },
1391+
};
1392+
1393+
static struct qcom_icc_bcm bcm_sn1 = {
1394+
.name = "SN1",
1395+
.keepalive = false,
1396+
.num_nodes = 1,
1397+
.nodes = { &qxs_imem },
1398+
};
1399+
1400+
static struct qcom_icc_bcm bcm_cn1 = {
1401+
.name = "CN1",
1402+
.keepalive = false,
1403+
.num_nodes = 8,
1404+
.nodes = { &qhm_qspi,
1405+
&xm_sdc2,
1406+
&xm_emmc,
1407+
&qhs_ahb2phy2,
1408+
&qhs_emmc_cfg,
1409+
&qhs_pdm,
1410+
&qhs_qspi,
1411+
&qhs_sdc2
1412+
},
1413+
};
1414+
1415+
static struct qcom_icc_bcm bcm_sn2 = {
1416+
.name = "SN2",
1417+
.keepalive = false,
1418+
.num_nodes = 2,
1419+
.nodes = { &qxm_pimem, &qns_gemnoc_gc },
1420+
};
1421+
1422+
static struct qcom_icc_bcm bcm_co2 = {
1423+
.name = "CO2",
1424+
.keepalive = false,
1425+
.num_nodes = 1,
1426+
.nodes = { &qnm_npu },
1427+
};
1428+
1429+
static struct qcom_icc_bcm bcm_sn3 = {
1430+
.name = "SN3",
1431+
.keepalive = false,
1432+
.num_nodes = 1,
1433+
.nodes = { &qxs_pimem },
1434+
};
1435+
1436+
static struct qcom_icc_bcm bcm_co3 = {
1437+
.name = "CO3",
1438+
.keepalive = false,
1439+
.num_nodes = 1,
1440+
.nodes = { &qxm_npu_dsp },
1441+
};
1442+
1443+
static struct qcom_icc_bcm bcm_sn4 = {
1444+
.name = "SN4",
1445+
.keepalive = false,
1446+
.num_nodes = 1,
1447+
.nodes = { &xs_qdss_stm },
1448+
};
1449+
1450+
static struct qcom_icc_bcm bcm_sn7 = {
1451+
.name = "SN7",
1452+
.keepalive = false,
1453+
.num_nodes = 1,
1454+
.nodes = { &qnm_aggre1_noc },
1455+
};
1456+
1457+
static struct qcom_icc_bcm bcm_sn9 = {
1458+
.name = "SN9",
1459+
.keepalive = false,
1460+
.num_nodes = 1,
1461+
.nodes = { &qnm_aggre2_noc },
1462+
};
1463+
1464+
static struct qcom_icc_bcm bcm_sn12 = {
1465+
.name = "SN12",
1466+
.keepalive = false,
1467+
.num_nodes = 1,
1468+
.nodes = { &qnm_gemnoc },
1469+
};
12631470

12641471
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
12651472
&bcm_cn1,

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