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Merge patch series "riscv: Add GENERIC_ENTRY support"
guoren@kernel.org <guoren@kernel.org> says: From: Guo Ren <guoren@linux.alibaba.com> The patches convert riscv to use the generic entry infrastructure from kernel/entry/*. Some optimization for entry.S with new .macro and merge ret_from_kernel_thread into ret_from_fork. * b4-shazam-merge: riscv: entry: Consolidate general regs saving/restoring riscv: entry: Consolidate ret_from_kernel_thread into ret_from_fork riscv: entry: Remove extra level wrappers of trace_hardirqs_{on,off} riscv: entry: Convert to generic entry riscv: entry: Add noinstr to prevent instrumentation inserted riscv: ptrace: Remove duplicate operation Link: https://lore.kernel.org/r/20230222033021.983168-1-guoren@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2 parents 4b74077 + 45b32b9 commit e45d6a5

20 files changed

Lines changed: 278 additions & 494 deletions

‎arch/riscv/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ config RISCV
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select GENERIC_ATOMIC64 if !64BIT
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select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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select GENERIC_EARLY_IOREMAP
63+
select GENERIC_ENTRY
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select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO
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select GENERIC_IDLE_POLL_SETUP
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select GENERIC_IOREMAP if MMU

‎arch/riscv/include/asm/asm-prototypes.h‎

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@@ -27,5 +27,7 @@ DECLARE_DO_ERROR_INFO(do_trap_break);
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asmlinkage unsigned long get_overflow_stack(void);
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asmlinkage void handle_bad_stack(struct pt_regs *regs);
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asmlinkage void do_page_fault(struct pt_regs *regs);
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asmlinkage void do_irq(struct pt_regs *regs);
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#endif /* _ASM_RISCV_PROTOTYPES_H */

‎arch/riscv/include/asm/asm.h‎

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@@ -69,6 +69,7 @@
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#endif
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#ifdef __ASSEMBLY__
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#include <asm/asm-offsets.h>
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/* Common assembly source macros */
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@@ -81,6 +82,66 @@
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.endr
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.endm
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85+
/* save all GPs except x1 ~ x5 */
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.macro save_from_x6_to_x31
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REG_S x6, PT_T1(sp)
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REG_S x7, PT_T2(sp)
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REG_S x8, PT_S0(sp)
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REG_S x9, PT_S1(sp)
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REG_S x10, PT_A0(sp)
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REG_S x11, PT_A1(sp)
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REG_S x12, PT_A2(sp)
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REG_S x13, PT_A3(sp)
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REG_S x14, PT_A4(sp)
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REG_S x15, PT_A5(sp)
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REG_S x16, PT_A6(sp)
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REG_S x17, PT_A7(sp)
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REG_S x18, PT_S2(sp)
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REG_S x19, PT_S3(sp)
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REG_S x20, PT_S4(sp)
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REG_S x21, PT_S5(sp)
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REG_S x22, PT_S6(sp)
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REG_S x23, PT_S7(sp)
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REG_S x24, PT_S8(sp)
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REG_S x25, PT_S9(sp)
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REG_S x26, PT_S10(sp)
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REG_S x27, PT_S11(sp)
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REG_S x28, PT_T3(sp)
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REG_S x29, PT_T4(sp)
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REG_S x30, PT_T5(sp)
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REG_S x31, PT_T6(sp)
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.endm
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/* restore all GPs except x1 ~ x5 */
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.macro restore_from_x6_to_x31
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REG_L x6, PT_T1(sp)
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REG_L x7, PT_T2(sp)
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REG_L x8, PT_S0(sp)
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REG_L x9, PT_S1(sp)
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REG_L x10, PT_A0(sp)
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REG_L x11, PT_A1(sp)
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REG_L x12, PT_A2(sp)
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REG_L x13, PT_A3(sp)
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REG_L x14, PT_A4(sp)
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REG_L x15, PT_A5(sp)
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REG_L x16, PT_A6(sp)
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REG_L x17, PT_A7(sp)
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REG_L x18, PT_S2(sp)
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REG_L x19, PT_S3(sp)
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REG_L x20, PT_S4(sp)
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REG_L x21, PT_S5(sp)
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REG_L x22, PT_S6(sp)
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REG_L x23, PT_S7(sp)
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REG_L x24, PT_S8(sp)
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REG_L x25, PT_S9(sp)
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REG_L x26, PT_S10(sp)
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REG_L x27, PT_S11(sp)
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REG_L x28, PT_T3(sp)
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REG_L x29, PT_T4(sp)
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REG_L x30, PT_T5(sp)
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REG_L x31, PT_T6(sp)
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_ASM_H */

‎arch/riscv/include/asm/csr.h‎

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Original file line numberDiff line numberDiff line change
@@ -40,7 +40,6 @@
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#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */
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#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */
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#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */
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#define SR_UXL_SHIFT 32
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#endif
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/* SATP flags */

‎arch/riscv/include/asm/entry-common.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_ENTRY_COMMON_H
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#define _ASM_RISCV_ENTRY_COMMON_H
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#include <asm/stacktrace.h>
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void handle_page_fault(struct pt_regs *regs);
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void handle_break(struct pt_regs *regs);
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#endif /* _ASM_RISCV_ENTRY_COMMON_H */

‎arch/riscv/include/asm/ptrace.h‎

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Original file line numberDiff line numberDiff line change
@@ -53,6 +53,9 @@ struct pt_regs {
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unsigned long orig_a0;
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};
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#define PTRACE_SYSEMU 0x1f
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#define PTRACE_SYSEMU_SINGLESTEP 0x20
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#ifdef CONFIG_64BIT
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#define REG_FMT "%016lx"
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#else
@@ -121,8 +124,6 @@ extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
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void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
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unsigned long frame_pointer);
124-
int do_syscall_trace_enter(struct pt_regs *regs);
125-
void do_syscall_trace_exit(struct pt_regs *regs);
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/**
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* regs_get_register() - get register value from its offset
@@ -172,6 +173,11 @@ static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
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return 0;
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}
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176+
static inline int regs_irqs_disabled(struct pt_regs *regs)
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{
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return !(regs->status & SR_PIE);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_PTRACE_H */

‎arch/riscv/include/asm/stacktrace.h‎

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Original file line numberDiff line numberDiff line change
@@ -16,4 +16,9 @@ extern void notrace walk_stackframe(struct task_struct *task, struct pt_regs *re
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extern void dump_backtrace(struct pt_regs *regs, struct task_struct *task,
1717
const char *loglvl);
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19+
static inline bool on_thread_stack(void)
20+
{
21+
return !(((unsigned long)(current->stack) ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
22+
}
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#endif /* _ASM_RISCV_STACKTRACE_H */

‎arch/riscv/include/asm/syscall.h‎

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@@ -74,5 +74,26 @@ static inline int syscall_get_arch(struct task_struct *task)
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#endif
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}
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typedef long (*syscall_t)(ulong, ulong, ulong, ulong, ulong, ulong, ulong);
78+
static inline void syscall_handler(struct pt_regs *regs, ulong syscall)
79+
{
80+
syscall_t fn;
81+
82+
#ifdef CONFIG_COMPAT
83+
if ((regs->status & SR_UXL) == SR_UXL_32)
84+
fn = compat_sys_call_table[syscall];
85+
else
86+
#endif
87+
fn = sys_call_table[syscall];
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89+
regs->a0 = fn(regs->orig_a0, regs->a1, regs->a2,
90+
regs->a3, regs->a4, regs->a5, regs->a6);
91+
}
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93+
static inline bool arch_syscall_is_vdso_sigreturn(struct pt_regs *regs)
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{
95+
return false;
96+
}
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7798
asmlinkage long sys_riscv_flush_icache(uintptr_t, uintptr_t, uintptr_t);
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#endif /* _ASM_RISCV_SYSCALL_H */

‎arch/riscv/include/asm/thread_info.h‎

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@@ -67,6 +67,7 @@ struct thread_info {
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long kernel_sp; /* Kernel stack pointer */
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long user_sp; /* User stack pointer */
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int cpu;
70+
unsigned long syscall_work; /* SYSCALL_WORK_ flags */
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};
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7273
/*
@@ -89,35 +90,23 @@ struct thread_info {
8990
* - pending work-to-be-done flags are in lowest half-word
9091
* - other flags in upper half-word(s)
9192
*/
92-
#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
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#define TIF_NOTIFY_RESUME 1 /* callback before returning to user */
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#define TIF_SIGPENDING 2 /* signal pending */
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#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
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#define TIF_RESTORE_SIGMASK 4 /* restore signal mask in do_signal() */
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#define TIF_MEMDIE 5 /* is terminating due to OOM killer */
98-
#define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */
99-
#define TIF_SYSCALL_AUDIT 7 /* syscall auditing */
100-
#define TIF_SECCOMP 8 /* syscall secure computing */
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#define TIF_NOTIFY_SIGNAL 9 /* signal notifications exist */
10299
#define TIF_UPROBE 10 /* uprobe breakpoint or singlestep */
103100
#define TIF_32BIT 11 /* compat-mode 32bit process */
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105-
#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
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#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
107103
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
108104
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
109-
#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
110-
#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
111-
#define _TIF_SECCOMP (1 << TIF_SECCOMP)
112105
#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL)
113106
#define _TIF_UPROBE (1 << TIF_UPROBE)
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115108
#define _TIF_WORK_MASK \
116109
(_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED | \
117110
_TIF_NOTIFY_SIGNAL | _TIF_UPROBE)
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119-
#define _TIF_SYSCALL_WORK \
120-
(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT | \
121-
_TIF_SECCOMP)
122-
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#endif /* _ASM_RISCV_THREAD_INFO_H */

‎arch/riscv/kernel/Makefile‎

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@@ -68,8 +68,6 @@ obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o
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obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
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obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
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71-
obj-$(CONFIG_TRACE_IRQFLAGS) += trace_irq.o
72-
7371
obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
7472
obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
7573
obj-$(CONFIG_RISCV_SBI) += sbi.o

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