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Daniel Miessalexdeucher
Daniel Miess
authored and
alexdeucher
committed
drm/amd/display: Enable physymclk RCO
[Why] Enable the last of the RCO options for dcn35 [How] Breakout RCO from dccg35_set_physymclk so that physymclk RCO can be set in dccg_init without disabling physymclk Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Daniel Miess <daniel.miess@amd.com> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 90f2f83 commit e4c33ff

5 files changed

Lines changed: 102 additions & 37 deletions

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‎drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c‎

Lines changed: 40 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -325,6 +325,43 @@ static void dccg35_set_dpstreamclk(
325325
}
326326
}
327327

328+
static void dccg35_set_physymclk_root_clock_gating(
329+
struct dccg *dccg,
330+
int phy_inst,
331+
bool enable)
332+
{
333+
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
334+
335+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
336+
return;
337+
338+
switch (phy_inst) {
339+
case 0:
340+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
341+
PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
342+
break;
343+
case 1:
344+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
345+
PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
346+
break;
347+
case 2:
348+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
349+
PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
350+
break;
351+
case 3:
352+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
353+
PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
354+
break;
355+
case 4:
356+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
357+
PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
358+
break;
359+
default:
360+
BREAK_TO_DEBUGGER();
361+
return;
362+
}
363+
}
364+
328365
static void dccg35_set_physymclk(
329366
struct dccg *dccg,
330367
int phy_inst,
@@ -340,84 +377,54 @@ static void dccg35_set_physymclk(
340377
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
341378
PHYASYMCLK_EN, 1,
342379
PHYASYMCLK_SRC_SEL, clk_src);
343-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
344-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
345-
PHYASYMCLK_ROOT_GATE_DISABLE, 1);
346380
} else {
347381
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
348382
PHYASYMCLK_EN, 0,
349383
PHYASYMCLK_SRC_SEL, 0);
350-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
351-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
352-
PHYASYMCLK_ROOT_GATE_DISABLE, 0);
353384
}
354385
break;
355386
case 1:
356387
if (force_enable) {
357388
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
358389
PHYBSYMCLK_EN, 1,
359390
PHYBSYMCLK_SRC_SEL, clk_src);
360-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
361-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
362-
PHYBSYMCLK_ROOT_GATE_DISABLE, 1);
363391
} else {
364392
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
365393
PHYBSYMCLK_EN, 0,
366394
PHYBSYMCLK_SRC_SEL, 0);
367-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
368-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
369-
PHYBSYMCLK_ROOT_GATE_DISABLE, 0);
370395
}
371396
break;
372397
case 2:
373398
if (force_enable) {
374399
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
375400
PHYCSYMCLK_EN, 1,
376401
PHYCSYMCLK_SRC_SEL, clk_src);
377-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
378-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
379-
PHYCSYMCLK_ROOT_GATE_DISABLE, 1);
380402
} else {
381403
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
382404
PHYCSYMCLK_EN, 0,
383405
PHYCSYMCLK_SRC_SEL, 0);
384-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
385-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
386-
PHYCSYMCLK_ROOT_GATE_DISABLE, 0);
387406
}
388407
break;
389408
case 3:
390409
if (force_enable) {
391410
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
392411
PHYDSYMCLK_EN, 1,
393412
PHYDSYMCLK_SRC_SEL, clk_src);
394-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
395-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
396-
PHYDSYMCLK_ROOT_GATE_DISABLE, 1);
397413
} else {
398414
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
399415
PHYDSYMCLK_EN, 0,
400416
PHYDSYMCLK_SRC_SEL, 0);
401-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
402-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
403-
PHYDSYMCLK_ROOT_GATE_DISABLE, 0);
404417
}
405418
break;
406419
case 4:
407420
if (force_enable) {
408421
REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
409422
PHYESYMCLK_EN, 1,
410423
PHYESYMCLK_SRC_SEL, clk_src);
411-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
412-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
413-
PHYESYMCLK_ROOT_GATE_DISABLE, 1);
414424
} else {
415425
REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
416426
PHYESYMCLK_EN, 0,
417427
PHYESYMCLK_SRC_SEL, 0);
418-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
419-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
420-
PHYESYMCLK_ROOT_GATE_DISABLE, 0);
421428
}
422429
break;
423430
default:
@@ -490,8 +497,8 @@ void dccg35_init(struct dccg *dccg)
490497

491498
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
492499
for (otg_inst = 0; otg_inst < 5; otg_inst++)
493-
dccg35_set_physymclk(dccg, otg_inst,
494-
PHYSYMCLK_FORCE_SRC_SYMCLK, false);
500+
dccg35_set_physymclk_root_clock_gating(dccg, otg_inst,
501+
false);
495502
/*
496503
dccg35_enable_global_fgcg_rep(
497504
dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits
@@ -756,6 +763,7 @@ static const struct dccg_funcs dccg35_funcs = {
756763
.disable_symclk32_le = dccg31_disable_symclk32_le,
757764
.set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,
758765
.set_physymclk = dccg35_set_physymclk,
766+
.set_physymclk_root_clock_gating = dccg35_set_physymclk_root_clock_gating,
759767
.set_dtbclk_dto = dccg35_set_dtbclk_dto,
760768
.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
761769
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

‎drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c‎

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -610,7 +610,23 @@ static struct dce_hwseq_registers hwseq_reg;
610610
HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
611611
HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
612612
HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
613-
HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh)
613+
HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
614+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
615+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
616+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
617+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
618+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
619+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
620+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
621+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
622+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
623+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
624+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
625+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
626+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
627+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
628+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
629+
HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh)
614630

615631
static const struct dce_hwseq_shift hwseq_shift = {
616632
HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
@@ -725,7 +741,7 @@ static const struct dc_debug_options debug_defaults_drv = {
725741
.symclk32_se = true,
726742
.symclk32_le = true,
727743
.symclk_fe = true,
728-
.physymclk = false, // Prevents eDP light up
744+
.physymclk = true,
729745
.dpiasymclk = true,
730746
}
731747
},

‎drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1183,7 +1183,23 @@ struct dce_hwseq_registers {
11831183
type LONO_FGCG_REP_DIS;\
11841184
type LONO_DISPCLK_GATE_DISABLE;\
11851185
type LONO_SOCCLK_GATE_DISABLE;\
1186-
type LONO_DMCUBCLK_GATE_DISABLE;
1186+
type LONO_DMCUBCLK_GATE_DISABLE;\
1187+
type SYMCLKA_FE_GATE_DISABLE;\
1188+
type SYMCLKB_FE_GATE_DISABLE;\
1189+
type SYMCLKC_FE_GATE_DISABLE;\
1190+
type SYMCLKD_FE_GATE_DISABLE;\
1191+
type SYMCLKE_FE_GATE_DISABLE;\
1192+
type HDMICHARCLK0_GATE_DISABLE;\
1193+
type SYMCLKA_GATE_DISABLE;\
1194+
type SYMCLKB_GATE_DISABLE;\
1195+
type SYMCLKC_GATE_DISABLE;\
1196+
type SYMCLKD_GATE_DISABLE;\
1197+
type SYMCLKE_GATE_DISABLE;\
1198+
type PHYASYMCLK_ROOT_GATE_DISABLE;\
1199+
type PHYBSYMCLK_ROOT_GATE_DISABLE;\
1200+
type PHYCSYMCLK_ROOT_GATE_DISABLE;\
1201+
type PHYDSYMCLK_ROOT_GATE_DISABLE;\
1202+
type PHYESYMCLK_ROOT_GATE_DISABLE;
11871203

11881204
struct dce_hwseq_shift {
11891205
HWSEQ_REG_FIELD_LIST(uint8_t)

‎drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c‎

Lines changed: 22 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,15 @@ void dcn35_init_hw(struct dc *dc)
146146
}
147147

148148
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
149-
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0x3F000000);
149+
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
150+
151+
/* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */
152+
REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,
153+
PHYBSYMCLK_ROOT_GATE_DISABLE, 1,
154+
PHYCSYMCLK_ROOT_GATE_DISABLE, 1,
155+
PHYDSYMCLK_ROOT_GATE_DISABLE, 1,
156+
PHYESYMCLK_ROOT_GATE_DISABLE, 1);
157+
150158
REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0x1f7c3fcf);
151159

152160
// Initialize the dccg
@@ -275,7 +283,19 @@ void dcn35_init_hw(struct dc *dc)
275283
if (!dc->debug.disable_clock_gate) {
276284
/* enable all DCN clock gating */
277285
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
278-
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
286+
287+
REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, 0,
288+
SYMCLKB_FE_GATE_DISABLE, 0,
289+
SYMCLKC_FE_GATE_DISABLE, 0,
290+
SYMCLKD_FE_GATE_DISABLE, 0,
291+
SYMCLKE_FE_GATE_DISABLE, 0);
292+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, 0);
293+
REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, 0,
294+
SYMCLKB_GATE_DISABLE, 0,
295+
SYMCLKC_GATE_DISABLE, 0,
296+
SYMCLKD_GATE_DISABLE, 0,
297+
SYMCLKE_GATE_DISABLE, 0);
298+
279299
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
280300
}
281301

‎drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,11 @@ struct dccg_funcs {
141141
enum physymclk_clock_source clk_src,
142142
bool force_enable);
143143

144+
void (*set_physymclk_root_clock_gating)(
145+
struct dccg *dccg,
146+
int phy_inst,
147+
bool enable);
148+
144149
void (*set_dtbclk_dto)(
145150
struct dccg *dccg,
146151
const struct dtbclk_dto_params *params);

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