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dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets
Some of the USB4 muxes, RCGs and resets were not initially described. Add indices for them to allow extending the driver. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251003-topic-hamoa_gcc_usb4-v2-1-61d27a14ee65@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Lines changed: 119 additions & 4 deletions

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‎Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml‎

Lines changed: 58 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,9 +32,36 @@ properties:
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- description: PCIe 5 pipe clock
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- description: PCIe 6a pipe clock
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- description: PCIe 6b pipe clock
35-
- description: USB QMP Phy 0 clock source
36-
- description: USB QMP Phy 1 clock source
37-
- description: USB QMP Phy 2 clock source
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- description: USB4_0 QMPPHY clock source
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- description: USB4_1 QMPPHY clock source
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- description: USB4_2 QMPPHY clock source
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- description: USB4_0 PHY DP0 GMUX clock source
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- description: USB4_0 PHY DP1 GMUX clock source
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- description: USB4_0 PHY PCIE PIPEGMUX clock source
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- description: USB4_0 PHY PIPEGMUX clock source
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- description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
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- description: USB4_1 PHY DP0 GMUX 2 clock source
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- description: USB4_1 PHY DP1 GMUX 2 clock source
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- description: USB4_1 PHY PCIE PIPEGMUX clock source
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- description: USB4_1 PHY PIPEGMUX clock source
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- description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
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- description: USB4_2 PHY DP0 GMUX 2 clock source
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- description: USB4_2 PHY DP1 GMUX 2 clock source
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- description: USB4_2 PHY PCIE PIPEGMUX clock source
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- description: USB4_2 PHY PIPEGMUX clock source
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- description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
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- description: USB4_0 PHY RX 0 clock source
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- description: USB4_0 PHY RX 1 clock source
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- description: USB4_1 PHY RX 0 clock source
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- description: USB4_1 PHY RX 1 clock source
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- description: USB4_2 PHY RX 0 clock source
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- description: USB4_2 PHY RX 1 clock source
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- description: USB4_0 PHY PCIE PIPE clock source
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- description: USB4_0 PHY max PIPE clock source
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- description: USB4_1 PHY PCIE PIPE clock source
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- description: USB4_1 PHY max PIPE clock source
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- description: USB4_2 PHY PCIE PIPE clock source
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- description: USB4_2 PHY max PIPE clock source
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power-domains:
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description:
@@ -67,7 +94,34 @@ examples:
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<&pcie6b_phy>,
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<&usb_1_ss0_qmpphy 0>,
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<&usb_1_ss1_qmpphy 1>,
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<&usb_1_ss2_qmpphy 2>;
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<&usb_1_ss2_qmpphy 2>,
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<&usb4_0_phy_dp0_gmux_clk>,
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<&usb4_0_phy_dp1_gmux_clk>,
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<&usb4_0_phy_pcie_pipegmux_clk>,
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<&usb4_0_phy_pipegmux_clk>,
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<&usb4_0_phy_sys_pcie_pipegmux_clk>,
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<&usb4_1_phy_dp0_gmux_2_clk>,
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<&usb4_1_phy_dp1_gmux_2_clk>,
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<&usb4_1_phy_pcie_pipegmux_clk>,
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<&usb4_1_phy_pipegmux_clk>,
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<&usb4_1_phy_sys_pcie_pipegmux_clk>,
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<&usb4_2_phy_dp0_gmux_2_clk>,
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<&usb4_2_phy_dp1_gmux_2_clk>,
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<&usb4_2_phy_pcie_pipegmux_clk>,
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<&usb4_2_phy_pipegmux_clk>,
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<&usb4_2_phy_sys_pcie_pipegmux_clk>,
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<&usb4_0_phy_rx_0_clk>,
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<&usb4_0_phy_rx_1_clk>,
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<&usb4_1_phy_rx_0_clk>,
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<&usb4_1_phy_rx_1_clk>,
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<&usb4_2_phy_rx_0_clk>,
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<&usb4_2_phy_rx_1_clk>,
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<&usb4_0_phy_pcie_pipe_clk>,
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<&usb4_0_phy_max_pipe_clk>,
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<&usb4_1_phy_pcie_pipe_clk>,
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<&usb4_1_phy_max_pipe_clk>,
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<&usb4_2_phy_pcie_pipe_clk>,
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<&usb4_2_phy_max_pipe_clk>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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#clock-cells = <1>;
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#reset-cells = <1>;

‎include/dt-bindings/clock/qcom,x1e80100-gcc.h‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,30 @@
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354
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#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355
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#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 356
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#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 357
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#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 358
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#define GCC_USB4_0_PHY_DP0_CLK_SRC 359
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#define GCC_USB4_0_PHY_DP1_CLK_SRC 360
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#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361
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#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 362
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#define GCC_USB4_0_PHY_RX0_CLK_SRC 363
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#define GCC_USB4_0_PHY_RX1_CLK_SRC 364
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#define GCC_USB4_0_PHY_SYS_CLK_SRC 365
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#define GCC_USB4_1_PHY_DP0_CLK_SRC 366
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#define GCC_USB4_1_PHY_DP1_CLK_SRC 367
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#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 368
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#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 369
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#define GCC_USB4_1_PHY_RX0_CLK_SRC 370
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#define GCC_USB4_1_PHY_RX1_CLK_SRC 371
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#define GCC_USB4_1_PHY_SYS_CLK_SRC 372
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#define GCC_USB4_2_PHY_DP0_CLK_SRC 373
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#define GCC_USB4_2_PHY_DP1_CLK_SRC 374
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#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 375
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#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 376
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#define GCC_USB4_2_PHY_RX0_CLK_SRC 377
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#define GCC_USB4_2_PHY_RX1_CLK_SRC 378
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#define GCC_USB4_2_PHY_SYS_CLK_SRC 379
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/* GCC power domains */
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#define GCC_PCIE_0_TUNNEL_GDSC 0
@@ -484,4 +508,41 @@
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#define GCC_VIDEO_BCR 87
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#define GCC_VIDEO_AXI0_CLK_ARES 88
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#define GCC_VIDEO_AXI1_CLK_ARES 89
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#define GCC_USB4_0_MISC_USB4_SYS_BCR 90
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#define GCC_USB4_0_MISC_RX_CLK_0_BCR 91
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#define GCC_USB4_0_MISC_RX_CLK_1_BCR 92
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#define GCC_USB4_0_MISC_USB_PIPE_BCR 93
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#define GCC_USB4_0_MISC_PCIE_PIPE_BCR 94
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#define GCC_USB4_0_MISC_TMU_BCR 95
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#define GCC_USB4_0_MISC_SB_IF_BCR 96
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#define GCC_USB4_0_MISC_HIA_MSTR_BCR 97
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#define GCC_USB4_0_MISC_AHB_BCR 98
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#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR 99
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#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR 100
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#define GCC_USB4_1_MISC_USB4_SYS_BCR 101
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#define GCC_USB4_1_MISC_RX_CLK_0_BCR 102
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#define GCC_USB4_1_MISC_RX_CLK_1_BCR 103
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#define GCC_USB4_1_MISC_USB_PIPE_BCR 104
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#define GCC_USB4_1_MISC_PCIE_PIPE_BCR 105
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#define GCC_USB4_1_MISC_TMU_BCR 106
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#define GCC_USB4_1_MISC_SB_IF_BCR 107
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#define GCC_USB4_1_MISC_HIA_MSTR_BCR 108
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#define GCC_USB4_1_MISC_AHB_BCR 109
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#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR 110
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#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR 111
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#define GCC_USB4_2_MISC_USB4_SYS_BCR 112
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#define GCC_USB4_2_MISC_RX_CLK_0_BCR 113
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#define GCC_USB4_2_MISC_RX_CLK_1_BCR 114
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#define GCC_USB4_2_MISC_USB_PIPE_BCR 115
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#define GCC_USB4_2_MISC_PCIE_PIPE_BCR 116
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#define GCC_USB4_2_MISC_TMU_BCR 117
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#define GCC_USB4_2_MISC_SB_IF_BCR 118
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#define GCC_USB4_2_MISC_HIA_MSTR_BCR 119
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#define GCC_USB4_2_MISC_AHB_BCR 120
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#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR 121
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#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR 122
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#define GCC_USB4PHY_PHY_PRIM_BCR 123
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#define GCC_USB4PHY_PHY_SEC_BCR 124
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#define GCC_USB4PHY_PHY_TERT_BCR 125
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#endif

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