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frankcrawfordgroeck
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hwmon: (it87) Test for chipset before entering configuration mode
Major part of the change for the new method to avoid chipset issues. The actual update does the following: 1) Lock the memory, but does not perform a SIO entry (previously it would have performed an SIO entry). 2) Attempt to read the chipID. This should be safe no matter which chip we have. 3) If step (2) fails, then perform SIO entry and retry chipID read. For older chips and on failure it acts similarly to prior to this patch. 4) Set the sio_data->type, similar to previously. 5) If we have not performed an SIO entry, and this is not a chip type with the NOCONF feature, then it will perform an SIO entry at this point. 6) Proceed with setup as prior to this patch. 7) Any following access to the SIO registers will invoke the SIO entry and SIO exit steps unless it is a chip with the NOCONF feature set. This was set up in the previous patches in this patchset. 8) Update to the exit based on if it had performed a SIO entry or not. Signed-off-by: Frank Crawford <frank@crawford.emu.id.au> Link: https://lore.kernel.org/r/20240428060653.2425296-4-frank@crawford.emu.id.au [groeck: s/intialised/initialized/] Signed-off-by: Guenter Roeck <linux@roeck-us.net>
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Lines changed: 47 additions & 5 deletions

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drivers/hwmon/it87.c

Lines changed: 47 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2667,23 +2667,53 @@ static const struct attribute_group it87_group_auto_pwm = {
26672667
.is_visible = it87_auto_pwm_is_visible,
26682668
};
26692669

2670+
/*
2671+
* Original explanation:
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* On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
2673+
* (IT8792E) needs to be in configuration mode before accessing the first
2674+
* due to a bug in IT8792E which otherwise results in LPC bus access errors.
2675+
* This needs to be done before accessing the first Super-IO chip since
2676+
* the second chip may have been accessed prior to loading this driver.
2677+
*
2678+
* The problem is also reported to affect IT8795E, which is used on X299 boards
2679+
* and has the same chip ID as IT8792E (0x8733). It also appears to affect
2680+
* systems with IT8790E, which is used on some Z97X-Gaming boards as well as
2681+
* Z87X-OC.
2682+
*
2683+
* From other information supplied:
2684+
* ChipIDs 0x8733, 0x8695 (early ID for IT87952E) and 0x8790 are initialized
2685+
* and left in configuration mode, and entering and/or exiting configuration
2686+
* mode is what causes the crash.
2687+
*
2688+
* The recommendation is to look up the chipID before doing any mode swap
2689+
* and then act accordingly.
2690+
*/
26702691
/* SuperIO detection - will change isa_address if a chip is found */
26712692
static int __init it87_find(int sioaddr, unsigned short *address,
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struct it87_sio_data *sio_data, int chip_cnt)
26732694
{
26742695
int err;
26752696
u16 chip_type;
26762697
const struct it87_devices *config = NULL;
2698+
bool enabled = false;
26772699

2678-
err = superio_enter(sioaddr, false);
2700+
/* First step, lock memory but don't enter configuration mode */
2701+
err = superio_enter(sioaddr, true);
26792702
if (err)
26802703
return err;
26812704

26822705
err = -ENODEV;
26832706
chip_type = superio_inw(sioaddr, DEVID);
2684-
/* check first for a valid chip before forcing chip id */
2685-
if (chip_type == 0xffff)
2686-
goto exit;
2707+
/* Check for a valid chip before forcing chip id */
2708+
if (chip_type == 0xffff) {
2709+
/* Enter configuration mode */
2710+
__superio_enter(sioaddr);
2711+
enabled = true;
2712+
/* and then try again */
2713+
chip_type = superio_inw(sioaddr, DEVID);
2714+
if (chip_type == 0xffff)
2715+
goto exit;
2716+
}
26872717

26882718
if (force_id_cnt == 1) {
26892719
/* If only one value given use for all chips */
@@ -2767,6 +2797,18 @@ static int __init it87_find(int sioaddr, unsigned short *address,
27672797

27682798
config = &it87_devices[sio_data->type];
27692799

2800+
/*
2801+
* If previously we didn't enter configuration mode and it isn't a
2802+
* chip we know is initialised in configuration mode, then enter
2803+
* configuration mode.
2804+
*
2805+
* I don't know if any such chips can exist but be defensive.
2806+
*/
2807+
if (!enabled && !has_noconf(config)) {
2808+
__superio_enter(sioaddr);
2809+
enabled = true;
2810+
}
2811+
27702812
superio_select(sioaddr, PME);
27712813
if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
27722814
pr_info("Device (chip %s ioreg 0x%x) not activated, skipping\n",
@@ -3144,7 +3186,7 @@ static int __init it87_find(int sioaddr, unsigned short *address,
31443186
}
31453187

31463188
exit:
3147-
superio_exit(sioaddr, config ? has_noconf(config) : false);
3189+
superio_exit(sioaddr, !enabled);
31483190
return err;
31493191
}
31503192

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