@@ -358,169 +358,8 @@ static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
358358 return 0 ;
359359}
360360
361- static void txgbe_gpio_irq_ack (struct irq_data * d )
362- {
363- struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
364- irq_hw_number_t hwirq = irqd_to_hwirq (d );
365- struct wx * wx = gpiochip_get_data (gc );
366- unsigned long flags ;
367-
368- raw_spin_lock_irqsave (& wx -> gpio_lock , flags );
369- wr32 (wx , WX_GPIO_EOI , BIT (hwirq ));
370- raw_spin_unlock_irqrestore (& wx -> gpio_lock , flags );
371- }
372-
373- static void txgbe_gpio_irq_mask (struct irq_data * d )
374- {
375- struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
376- irq_hw_number_t hwirq = irqd_to_hwirq (d );
377- struct wx * wx = gpiochip_get_data (gc );
378- unsigned long flags ;
379-
380- gpiochip_disable_irq (gc , hwirq );
381-
382- raw_spin_lock_irqsave (& wx -> gpio_lock , flags );
383- wr32m (wx , WX_GPIO_INTMASK , BIT (hwirq ), BIT (hwirq ));
384- raw_spin_unlock_irqrestore (& wx -> gpio_lock , flags );
385- }
386-
387- static void txgbe_gpio_irq_unmask (struct irq_data * d )
388- {
389- struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
390- irq_hw_number_t hwirq = irqd_to_hwirq (d );
391- struct wx * wx = gpiochip_get_data (gc );
392- unsigned long flags ;
393-
394- gpiochip_enable_irq (gc , hwirq );
395-
396- raw_spin_lock_irqsave (& wx -> gpio_lock , flags );
397- wr32m (wx , WX_GPIO_INTMASK , BIT (hwirq ), 0 );
398- raw_spin_unlock_irqrestore (& wx -> gpio_lock , flags );
399- }
400-
401- static void txgbe_toggle_trigger (struct gpio_chip * gc , unsigned int offset )
402- {
403- struct wx * wx = gpiochip_get_data (gc );
404- u32 pol , val ;
405-
406- pol = rd32 (wx , WX_GPIO_POLARITY );
407- val = rd32 (wx , WX_GPIO_EXT );
408-
409- if (val & BIT (offset ))
410- pol &= ~BIT (offset );
411- else
412- pol |= BIT (offset );
413-
414- wr32 (wx , WX_GPIO_POLARITY , pol );
415- }
416-
417- static int txgbe_gpio_set_type (struct irq_data * d , unsigned int type )
418- {
419- struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
420- irq_hw_number_t hwirq = irqd_to_hwirq (d );
421- struct wx * wx = gpiochip_get_data (gc );
422- u32 level , polarity , mask ;
423- unsigned long flags ;
424-
425- mask = BIT (hwirq );
426-
427- if (type & IRQ_TYPE_LEVEL_MASK ) {
428- level = 0 ;
429- irq_set_handler_locked (d , handle_level_irq );
430- } else {
431- level = mask ;
432- irq_set_handler_locked (d , handle_edge_irq );
433- }
434-
435- if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH )
436- polarity = mask ;
437- else
438- polarity = 0 ;
439-
440- raw_spin_lock_irqsave (& wx -> gpio_lock , flags );
441-
442- wr32m (wx , WX_GPIO_INTEN , mask , mask );
443- wr32m (wx , WX_GPIO_INTTYPE_LEVEL , mask , level );
444- if (type == IRQ_TYPE_EDGE_BOTH )
445- txgbe_toggle_trigger (gc , hwirq );
446- else
447- wr32m (wx , WX_GPIO_POLARITY , mask , polarity );
448-
449- raw_spin_unlock_irqrestore (& wx -> gpio_lock , flags );
450-
451- return 0 ;
452- }
453-
454- static const struct irq_chip txgbe_gpio_irq_chip = {
455- .name = "txgbe-gpio-irq" ,
456- .irq_ack = txgbe_gpio_irq_ack ,
457- .irq_mask = txgbe_gpio_irq_mask ,
458- .irq_unmask = txgbe_gpio_irq_unmask ,
459- .irq_set_type = txgbe_gpio_set_type ,
460- .flags = IRQCHIP_IMMUTABLE ,
461- GPIOCHIP_IRQ_RESOURCE_HELPERS ,
462- };
463-
464- irqreturn_t txgbe_gpio_irq_handler (int irq , void * data )
465- {
466- struct txgbe * txgbe = data ;
467- struct wx * wx = txgbe -> wx ;
468- irq_hw_number_t hwirq ;
469- unsigned long gpioirq ;
470- struct gpio_chip * gc ;
471- unsigned long flags ;
472-
473- gpioirq = rd32 (wx , WX_GPIO_INTSTATUS );
474-
475- gc = txgbe -> gpio ;
476- for_each_set_bit (hwirq , & gpioirq , gc -> ngpio ) {
477- int gpio = irq_find_mapping (gc -> irq .domain , hwirq );
478- struct irq_data * d = irq_get_irq_data (gpio );
479- u32 irq_type = irq_get_trigger_type (gpio );
480-
481- txgbe_gpio_irq_ack (d );
482- handle_nested_irq (gpio );
483-
484- if ((irq_type & IRQ_TYPE_SENSE_MASK ) == IRQ_TYPE_EDGE_BOTH ) {
485- raw_spin_lock_irqsave (& wx -> gpio_lock , flags );
486- txgbe_toggle_trigger (gc , hwirq );
487- raw_spin_unlock_irqrestore (& wx -> gpio_lock , flags );
488- }
489- }
490-
491- return IRQ_HANDLED ;
492- }
493-
494- void txgbe_reinit_gpio_intr (struct wx * wx )
495- {
496- struct txgbe * txgbe = wx -> priv ;
497- irq_hw_number_t hwirq ;
498- unsigned long gpioirq ;
499- struct gpio_chip * gc ;
500- unsigned long flags ;
501-
502- /* for gpio interrupt pending before irq enable */
503- gpioirq = rd32 (wx , WX_GPIO_INTSTATUS );
504-
505- gc = txgbe -> gpio ;
506- for_each_set_bit (hwirq , & gpioirq , gc -> ngpio ) {
507- int gpio = irq_find_mapping (gc -> irq .domain , hwirq );
508- struct irq_data * d = irq_get_irq_data (gpio );
509- u32 irq_type = irq_get_trigger_type (gpio );
510-
511- txgbe_gpio_irq_ack (d );
512-
513- if ((irq_type & IRQ_TYPE_SENSE_MASK ) == IRQ_TYPE_EDGE_BOTH ) {
514- raw_spin_lock_irqsave (& wx -> gpio_lock , flags );
515- txgbe_toggle_trigger (gc , hwirq );
516- raw_spin_unlock_irqrestore (& wx -> gpio_lock , flags );
517- }
518- }
519- }
520-
521361static int txgbe_gpio_init (struct txgbe * txgbe )
522362{
523- struct gpio_irq_chip * girq ;
524363 struct gpio_chip * gc ;
525364 struct device * dev ;
526365 struct wx * wx ;
@@ -550,11 +389,6 @@ static int txgbe_gpio_init(struct txgbe *txgbe)
550389 gc -> direction_input = txgbe_gpio_direction_in ;
551390 gc -> direction_output = txgbe_gpio_direction_out ;
552391
553- girq = & gc -> irq ;
554- gpio_irq_chip_set_chip (girq , & txgbe_gpio_irq_chip );
555- girq -> default_type = IRQ_TYPE_NONE ;
556- girq -> handler = handle_bad_irq ;
557-
558392 ret = devm_gpiochip_add_data (dev , gc , wx );
559393 if (ret )
560394 return ret ;
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