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Merge tag 'spi-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "The highlight here is that David Lechner has added support for multi-lane SPI devices. Unlike the existing dual/quad SPI support this is for devices (typically ADCs/DACs) which support multiple independent data streams over multiple data lanes, instead of sending one data stream N times as fast they simultaneously transfer N different data streams. This is very similar to the case where multiple devices are grouped together but in this case it's a single device in a way that's visible to software. Otherwise there's been quite a bit of work on existing drivers, both cleanup and feature improvement, and a reasonable collection of new drivers. - Support for multi-lane SPI devices - Preparatory work for some memory mapped flash improvements that will happen in the MTD subsystem - Several conversions to fwnode APIs - A bunch of cleanup and hardening work on the ST drivers - Support for DMA mode on Renesas RZV2H and i.MX target mode - Support for ATCSPI200, AXIADO AX300, NXP XPI and Renesas RZ/N1" * tag 'spi-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (108 commits) spi: tools: Add include folder to .gitignore spi: cadence-qspi: Add support for the Renesas RZ/N1 controller spi: cadence-qspi: Kill cqspi_jh7110_clk_init spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list spi: geni-qcom: Add target abort support spi: geni-qcom: Drop unused msg parameter from timeout handlers spi: geni-qcom: Fix abort sequence execution for serial engine errors spi: geni-qcom: Improve target mode allocation by using proper allocation functions spi: xilinx: use device property accessors. dt-bindings: spi: Add binding for Faraday FTSSP010 spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE spi: dt-bindings: adi,axi-spi-engine: add multi-lane support spi: Documentation: add page on multi-lane support spi: add multi_lane_mode field to struct spi_transfer spi: support controllers with multiple data lanes spi: dt-bindings: add spi-{tx,rx}-lane-map properties spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays spi: dw: Remove not-going-to-be-supported code for Baikal SoC spi: cadence-qspi: Use a default value for cdns,fifo-width spi: cadence-qspi: Make sure write protection is disabled ...
2 parents f6c4248 + 5af56f3 commit e86dda7

141 files changed

Lines changed: 5800 additions & 1199 deletions

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Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,9 @@ properties:
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spi-cpol: true
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spi-rx-bus-width:
37-
minimum: 0
38-
maximum: 1
37+
items:
38+
minimum: 0
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maximum: 1
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dc-gpios:
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maxItems: 1

Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml

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Original file line numberDiff line numberDiff line change
@@ -37,7 +37,15 @@ properties:
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maximum: 102040816
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spi-rx-bus-width:
40-
enum: [1, 2, 4]
40+
maxItems: 2
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# all lanes must have the same width
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oneOf:
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- contains:
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const: 1
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- contains:
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const: 2
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- contains:
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const: 4
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vdd-5v-supply: true
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vdd-1v8-supply: true
@@ -88,6 +96,18 @@ oneOf:
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unevaluatedProperties: false
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- adi,ad4030-24
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- adi,ad4032-24
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then:
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properties:
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spi-rx-bus-width:
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maxItems: 1
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91111
examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
@@ -108,3 +128,23 @@ examples:
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reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
109129
};
110130
};
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- |
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#include <dt-bindings/gpio/gpio.h>
133+
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spi {
135+
#address-cells = <1>;
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#size-cells = <0>;
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adc@0 {
139+
compatible = "adi,ad4630-24";
140+
reg = <0>;
141+
spi-max-frequency = <80000000>;
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spi-rx-bus-width = <4>, <4>;
143+
vdd-5v-supply = <&supply_5V>;
144+
vdd-1v8-supply = <&supply_1_8V>;
145+
vio-supply = <&supply_1_8V>;
146+
ref-supply = <&supply_5V>;
147+
cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
148+
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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};
150+
};

Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml

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@@ -38,8 +38,9 @@ properties:
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spi-cpha: true
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spi-rx-bus-width:
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minimum: 1
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maximum: 4
41+
items:
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minimum: 1
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maximum: 4
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avdd-supply:
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description: Analog power supply.

Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml

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@@ -70,6 +70,21 @@ required:
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unevaluatedProperties: false
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73+
patternProperties:
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"^.*@[0-9a-f]+":
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type: object
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77+
properties:
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spi-rx-bus-width:
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maxItems: 8
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items:
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enum: [0, 1]
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83+
spi-tx-bus-width:
84+
maxItems: 8
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items:
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enum: [0, 1]
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examples:
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- |
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spi@44a00000 {

Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml

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@@ -55,10 +55,12 @@ patternProperties:
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maximum: 4
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spi-rx-bus-width:
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const: 1
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items:
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- const: 1
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spi-tx-bus-width:
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const: 1
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items:
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- const: 1
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required:
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- compatible

Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml

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@@ -81,10 +81,12 @@ patternProperties:
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maximum: 4
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spi-rx-bus-width:
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const: 1
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items:
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- const: 1
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spi-tx-bus-width:
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const: 1
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items:
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- const: 1
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required:
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- compatible
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@@ -0,0 +1,87 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
4+
$id: http://devicetree.org/schemas/spi/andestech,ae350-spi.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Andes ATCSPI200 SPI controller
8+
9+
maintainers:
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- CL Wang <cl634@andestech.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- andestech,qilai-spi
18+
- const: andestech,ae350-spi
19+
- const: andestech,ae350-spi
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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num-cs:
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description: Number of chip selects supported
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maxItems: 1
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dmas:
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items:
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- description: Transmit FIFO DMA channel
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- description: Receive FIFO DMA channel
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dma-names:
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items:
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- const: tx
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- const: rx
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patternProperties:
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"@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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spi-rx-bus-width:
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items:
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- enum: [1, 4]
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spi-tx-bus-width:
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items:
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- enum: [1, 4]
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allOf:
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- $ref: spi-controller.yaml#
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required:
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- compatible
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- reg
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- clocks
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- dmas
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- dma-names
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unevaluatedProperties: false
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examples:
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- |
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spi@f0b00000 {
70+
compatible = "andestech,ae350-spi";
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reg = <0xf0b00000 0x100>;
72+
clocks = <&clk_spi>;
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dmas = <&dma0 0>, <&dma0 1>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
80+
compatible = "jedec,spi-nor";
81+
reg = <0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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spi-cpol;
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spi-cpha;
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};
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};

Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml

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- const: atmel,at91rm9200-spi
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- items:
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- enum:
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- microchip,lan9691-spi
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- microchip,sam9x60-spi
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- microchip,sam9x7-spi
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- microchip,sama7d65-spi
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
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---
4+
$id: http://devicetree.org/schemas/spi/axiado,ax3000-spi.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Axiado AX3000 SoC SPI controller
8+
9+
maintainers:
10+
- Vladimir Moravcevic <vmoravcevic@axiado.com>
11+
- Tzu-Hao Wei <twei@axiado.com>
12+
- Swark Yang <syang@axiado.com>
13+
- Prasad Bolisetty <pbolisetty@axiado.com>
14+
15+
allOf:
16+
- $ref: spi-controller.yaml#
17+
18+
properties:
19+
compatible:
20+
enum:
21+
- axiado,ax3000-spi
22+
23+
reg:
24+
maxItems: 1
25+
26+
interrupts:
27+
maxItems: 1
28+
29+
clock-names:
30+
items:
31+
- const: ref
32+
- const: pclk
33+
34+
clocks:
35+
maxItems: 2
36+
37+
num-cs:
38+
description: |
39+
Number of chip selects used.
40+
$ref: /schemas/types.yaml#/definitions/uint32
41+
minimum: 1
42+
maximum: 4
43+
default: 4
44+
45+
required:
46+
- compatible
47+
- reg
48+
- interrupts
49+
- clock-names
50+
- clocks
51+
52+
unevaluatedProperties: false
53+
54+
examples:
55+
- |
56+
#include <dt-bindings/interrupt-controller/irq.h>
57+
#include <dt-bindings/interrupt-controller/arm-gic.h>
58+
59+
soc {
60+
#address-cells = <2>;
61+
#size-cells = <2>;
62+
63+
spi@80510000 {
64+
compatible = "axiado,ax3000-spi";
65+
reg = <0x00 0x80510000 0x00 0x1000>;
66+
clock-names = "ref", "pclk";
67+
clocks = <&spi_clk>, <&apb_pclk>;
68+
interrupt-parent = <&gic500>;
69+
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
70+
num-cs = <4>;
71+
};
72+
};
73+
...

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

Lines changed: 18 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,20 @@ allOf:
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cdns,fifo-depth:
6262
enum: [ 128, 256 ]
6363
default: 128
64+
- if:
65+
properties:
66+
compatible:
67+
contains:
68+
const: renesas,rzn1-qspi
69+
then:
70+
properties:
71+
cdns,trigger-address: false
72+
cdns,fifo-depth: false
73+
cdns,fifo-width: false
74+
else:
75+
required:
76+
- cdns,trigger-address
77+
- cdns,fifo-depth
6478

6579
properties:
6680
compatible:
@@ -80,6 +94,9 @@ properties:
8094
# controllers are meant to be used with flashes of all kinds,
8195
# ie. also NAND flashes, not only NOR flashes.
8296
- const: cdns,qspi-nor
97+
- items:
98+
- const: renesas,r9a06g032-qspi
99+
- const: renesas,rzn1-qspi
83100
- const: cdns,qspi-nor
84101
deprecated: true
85102

@@ -163,16 +180,14 @@ required:
163180
- reg
164181
- interrupts
165182
- clocks
166-
- cdns,fifo-width
167-
- cdns,trigger-address
168183
- '#address-cells'
169184
- '#size-cells'
170185

171186
unevaluatedProperties: false
172187

173188
examples:
174189
- |
175-
qspi: spi@ff705000 {
190+
spi@ff705000 {
176191
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
177192
#address-cells = <1>;
178193
#size-cells = <0>;

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