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bebarinobebarino
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Merge branches 'clk-allwinner', 'clk-amlogic' and 'clk-qcom' into clk-next
* clk-allwinner: clk: sunxi-ng: add support for the A523/T527 PRCM CCU clk: sunxi-ng: a523: add reset lines clk: sunxi-ng: a523: add bus clock gates clk: sunxi-ng: a523: remaining mod clocks clk: sunxi-ng: a523: add USB mod clocks clk: sunxi-ng: a523: add interface mod clocks clk: sunxi-ng: a523: add system mod clocks clk: sunxi-ng: a523: add video mod clocks clk: sunxi-ng: a523: Add support for bus clocks clk: sunxi-ng: Add support for the A523/T527 CCU PLLs dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs clk: sunxi-ng: Add support for update bit clk: sunxi-ng: mp: provide wrappers for setting feature flags clk: sunxi-ng: mp: introduce dual-divider clock clk: sunxi-ng: h616: Reparent GPU clock during frequency changes clk: sunxi-ng: h616: Add clock/reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset * clk-amlogic: clk: amlogic: a1: fix a typo clk: amlogic: gxbb: drop non existing 32k clock parent clk: amlogic: gxbb: drop incorrect flag on 32k clock clk: amlogic: g12b: fix cluster A parent data clk: amlogic: g12a: fix mmc A peripheral clock * clk-qcom: (41 commits) clk: qcom: Add NSS clock Controller driver for IPQ9574 clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 dt-bindings: clock: qcom: Add compatible for QCM6490 boards clk: qcom: gdsc: Update the status poll timeout for GDSC clk: qcom: gdsc: Set retain_ff before moving to HW CTRL clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable() clk: qcom: videocc: Constify 'struct qcom_cc_desc' clk: qcom: gpucc: Constify 'struct qcom_cc_desc' clk: qcom: dispcc: Constify 'struct qcom_cc_desc' clk: qcom: camcc: Constify 'struct qcom_cc_desc' dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover clk: qcom: Add support for Video Clock Controller on QCS8300 clk: qcom: Add support for GPU Clock Controller on QCS8300 ...
4 parents 3ce2e14 + 054b4ea + 0a1f6dd + f00618a commit e988adc

116 files changed

Lines changed: 6536 additions & 237 deletions

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‎Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/allwinner,sun55i-a523-ccu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A523 Clock Control Unit
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9+
maintainers:
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- Andre Przywara <andre.przywara@arm.com>
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12+
properties:
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
18+
19+
compatible:
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enum:
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- allwinner,sun55i-a523-ccu
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- allwinner,sun55i-a523-r-ccu
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reg:
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maxItems: 1
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27+
clocks:
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minItems: 4
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maxItems: 5
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31+
clock-names:
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minItems: 4
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maxItems: 5
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required:
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- "#clock-cells"
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- "#reset-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- allwinner,sun55i-a523-ccu
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then:
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properties:
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clocks:
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items:
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- description: High Frequency Oscillator (usually at 24MHz)
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- description: Low Frequency Oscillator (usually at 32kHz)
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- description: Internal Oscillator
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- description: Low Frequency Oscillator fanout
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clock-names:
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items:
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- const: hosc
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- const: losc
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- const: iosc
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- const: losc-fanout
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- if:
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properties:
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compatible:
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enum:
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- allwinner,sun55i-a523-r-ccu
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then:
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properties:
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clocks:
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items:
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- description: High Frequency Oscillator (usually at 24MHz)
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- description: Low Frequency Oscillator (usually at 32kHz)
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- description: Internal Oscillator
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- description: Peripherals PLL
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- description: Audio PLL
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clock-names:
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items:
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- const: hosc
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- const: losc
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- const: iosc
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- const: pll-periph
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- const: pll-audio
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additionalProperties: false
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examples:
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- |
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clock-controller@2001000 {
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compatible = "allwinner,sun55i-a523-ccu";
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reg = <0x02001000 0x1000>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>, <&r_ccu 1>;
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clock-names = "hosc", "losc", "iosc", "losc-fanout";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gpucc.yaml‎

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@@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller
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99
maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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- Imran Shaik <quic_imrashai@quicinc.com>
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description: |
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Qualcomm graphics clock control module provides the clocks, resets and power
@@ -23,10 +24,12 @@ description: |
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include/dt-bindings/clock/qcom,gpucc-sm8150.h
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include/dt-bindings/clock/qcom,gpucc-sm8250.h
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include/dt-bindings/clock/qcom,gpucc-sm8350.h
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include/dt-bindings/clock/qcom,qcs8300-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,qcs8300-gpucc
3033
- qcom,sdm845-gpucc
3134
- qcom,sa8775p-gpucc
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- qcom,sc7180-gpucc

‎Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
8+
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Anusha Rao <quic_anusha@quicinc.com>
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13+
description: |
14+
Qualcomm networking sub system clock control module provides the clocks,
15+
resets on IPQ9574
16+
17+
See also::
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include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19+
include/dt-bindings/reset/qcom,ipq9574-nsscc.h
20+
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properties:
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compatible:
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const: qcom,ipq9574-nsscc
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clocks:
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items:
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- description: Board XO source
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- description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
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- description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
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- description: GCC GPLL0 OUT AUX clock source
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- description: Uniphy0 NSS Rx clock source
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- description: Uniphy0 NSS Tx clock source
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- description: Uniphy1 NSS Rx clock source
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- description: Uniphy1 NSS Tx clock source
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- description: Uniphy2 NSS Rx clock source
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- description: Uniphy2 NSS Tx clock source
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- description: GCC NSSCC clock source
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'#interconnect-cells':
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const: 1
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clock-names:
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items:
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- const: xo
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- const: nss_1200
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- const: ppe_353
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- const: gpll0_out
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- const: uniphy0_rx
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- const: uniphy0_tx
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- const: uniphy1_rx
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- const: uniphy1_tx
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- const: uniphy2_rx
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- const: uniphy2_tx
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- const: bus
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required:
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- compatible
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- clocks
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- clock-names
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
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clock-controller@39b00000 {
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compatible = "qcom,ipq9574-nsscc";
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reg = <0x39b00000 0x80000>;
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clocks = <&xo_board_clk>,
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<&cmn_pll NSS_1200MHZ_CLK>,
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<&cmn_pll PPE_353MHZ_CLK>,
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<&gcc GPLL0_OUT_AUX>,
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<&uniphy 0>,
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<&uniphy 1>,
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<&uniphy 2>,
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<&uniphy 3>,
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<&uniphy 4>,
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<&uniphy 5>,
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<&gcc GCC_NSSCC_CLK>;
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clock-names = "xo",
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"nss_1200",
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"ppe_353",
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"gpll0_out",
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"uniphy0_rx",
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"uniphy0_tx",
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"uniphy1_rx",
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"uniphy1_tx",
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"uniphy2_rx",
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"uniphy2_tx",
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"bus";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml‎

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@@ -44,6 +44,7 @@ properties:
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- qcom,rpmcc-msm8998
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- qcom,rpmcc-qcm2290
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- qcom,rpmcc-qcs404
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- qcom,rpmcc-sdm429
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- qcom,rpmcc-sdm660
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- qcom,rpmcc-sm6115
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- qcom,rpmcc-sm6125
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- qcom,rpmcc-msm8998
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- qcom,rpmcc-qcm2290
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- qcom,rpmcc-qcs404
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- qcom,rpmcc-sdm429
126128
- qcom,rpmcc-sdm660
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- qcom,rpmcc-sm6115
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- qcom,rpmcc-sm6125

‎Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml‎

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@@ -8,16 +8,20 @@ title: Qualcomm Camera Clock & Reset Controller on SA8775P
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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- Imran Shaik <quic_imrashai@quicinc.com>
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1213
description: |
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Qualcomm camera clock control module provides the clocks, resets and power
1415
domains on SA8775p.
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16-
See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
17+
See also:
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include/dt-bindings/clock/qcom,qcs8300-camcc.h
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include/dt-bindings/clock/qcom,sa8775p-camcc.h
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properties:
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compatible:
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enum:
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- qcom,qcs8300-camcc
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- qcom,sa8775p-camcc
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clocks:

‎Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml‎

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properties:
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compatible:
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enum:
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- qcom,qcs8300-videocc
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- qcom,sa8775p-videocc
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clocks:

‎Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml‎

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properties:
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compatible:
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enum:
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- qcom,qcm6490-lpassaudiocc
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- qcom,sc7280-lpassaoncc
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- qcom,sc7280-lpassaudiocc
2526
- qcom,sc7280-lpasscorecc
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properties:
6970
compatible:
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contains:
71-
const: qcom,sc7280-lpassaudiocc
72+
enum:
73+
- qcom,qcm6490-lpassaudiocc
74+
- qcom,sc7280-lpassaudiocc
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7376
then:
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properties:

‎Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml‎

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- qcom,sc8280xp-camcc
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- qcom,sm8450-camcc
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- qcom,sm8550-camcc
67-
- qcom,x1e80100-camcc
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then:
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required:
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- required-opps

‎Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml‎

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- description: A phandle to the MMCX power-domain
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4242
required-opps:
43-
maxItems: 1
44-
description:
45-
A phandle to an OPP node describing MMCX performance points.
43+
items:
44+
- description: A phandle to an OPP node describing MXC performance points
45+
- description: A phandle to an OPP node describing MMCX performance points
4646

4747
required:
4848
- compatible
@@ -66,7 +66,8 @@ examples:
6666
<&sleep_clk>;
6767
power-domains = <&rpmhpd RPMHPD_MXC>,
6868
<&rpmhpd RPMHPD_MMCX>;
69-
required-opps = <&rpmhpd_opp_low_svs>;
69+
required-opps = <&rpmhpd_opp_low_svs>,
70+
<&rpmhpd_opp_low_svs>;
7071
#clock-cells = <1>;
7172
#reset-cells = <1>;
7273
#power-domain-cells = <1>;

‎drivers/clk/meson/a1-pll.c‎

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@@ -356,7 +356,7 @@ static struct platform_driver a1_pll_clkc_driver = {
356356
};
357357
module_platform_driver(a1_pll_clkc_driver);
358358

359-
MODULE_DESCRIPTION("Amlogic S4 PLL Clock Controller driver");
359+
MODULE_DESCRIPTION("Amlogic A1 PLL Clock Controller driver");
360360
MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
361361
MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
362362
MODULE_LICENSE("GPL");

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