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konradybciorobclark
konradybcio
authored and
robclark
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drm/msm/a6xx: Mostly implement A7xx gpu_state
Provide the necessary alternations to mostly support state dumping on A7xx. Newer GPUs will probably require more changes here. Crashdumper and debugbus remain untested. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559289/ Signed-off-by: Rob Clark <robdclark@chromium.org>
1 parent 88a0997 commit e997ae5

2 files changed

Lines changed: 110 additions & 3 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c‎

Lines changed: 51 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -948,6 +948,18 @@ static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)
948948
return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14;
949949
}
950950

951+
static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu)
952+
{
953+
/*
954+
* The value at CP_ROQ_THRESHOLDS_2[20:31] is in 4dword units.
955+
* That register however is not directly accessible from APSS on A7xx.
956+
* Program the SQE_UCODE_DBG_ADDR with offset=0x70d3 and read the value.
957+
*/
958+
gpu_write(gpu, REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 0x70d3);
959+
960+
return 4 * (gpu_read(gpu, REG_A6XX_CP_SQE_UCODE_DBG_DATA) >> 20);
961+
}
962+
951963
/* Read a block of data from an indexed register pair */
952964
static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
953965
struct a6xx_gpu_state *a6xx_state,
@@ -1019,8 +1031,40 @@ static void a6xx_get_indexed_registers(struct msm_gpu *gpu,
10191031

10201032
/* Restore the size in the hardware */
10211033
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size);
1034+
}
1035+
1036+
static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
1037+
struct a6xx_gpu_state *a6xx_state)
1038+
{
1039+
int i, indexed_count, mempool_count;
1040+
1041+
indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
1042+
mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed);
10221043

1023-
a6xx_state->nr_indexed_regs = count;
1044+
a6xx_state->indexed_regs = state_kcalloc(a6xx_state,
1045+
indexed_count + mempool_count,
1046+
sizeof(*a6xx_state->indexed_regs));
1047+
if (!a6xx_state->indexed_regs)
1048+
return;
1049+
1050+
a6xx_state->nr_indexed_regs = indexed_count + mempool_count;
1051+
1052+
/* First read the common regs */
1053+
for (i = 0; i < indexed_count; i++)
1054+
a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_indexed_reglist[i],
1055+
&a6xx_state->indexed_regs[i]);
1056+
1057+
gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2));
1058+
gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, 0, BIT(2));
1059+
1060+
/* Get the contents of the CP_BV mempool */
1061+
for (i = 0; i < mempool_count; i++)
1062+
a6xx_get_indexed_regs(gpu, a6xx_state, a7xx_cp_bv_mempool_indexed,
1063+
&a6xx_state->indexed_regs[indexed_count - 1 + i]);
1064+
1065+
gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0);
1066+
gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0);
1067+
return;
10241068
}
10251069

10261070
struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
@@ -1056,6 +1100,12 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
10561100
return &a6xx_state->base;
10571101

10581102
/* Get the banks of indexed registers */
1103+
if (adreno_is_a7xx(adreno_gpu)) {
1104+
a7xx_get_indexed_registers(gpu, a6xx_state);
1105+
/* Further codeflow is untested on A7xx. */
1106+
return &a6xx_state->base;
1107+
}
1108+
10591109
a6xx_get_indexed_registers(gpu, a6xx_state);
10601110

10611111
/*

‎drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h‎

Lines changed: 59 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -338,6 +338,28 @@ static const struct a6xx_registers a6xx_vbif_reglist =
338338
static const struct a6xx_registers a6xx_gbif_reglist =
339339
REGS(a6xx_gbif_registers, 0, 0);
340340

341+
static const u32 a7xx_ahb_registers[] = {
342+
/* RBBM_STATUS */
343+
0x210, 0x210,
344+
/* RBBM_STATUS2-3 */
345+
0x212, 0x213,
346+
};
347+
348+
static const u32 a7xx_gbif_registers[] = {
349+
0x3c00, 0x3c0b,
350+
0x3c40, 0x3c42,
351+
0x3c45, 0x3c47,
352+
0x3c49, 0x3c4a,
353+
0x3cc0, 0x3cd1,
354+
};
355+
356+
static const struct a6xx_registers a7xx_ahb_reglist[] = {
357+
REGS(a7xx_ahb_registers, 0, 0),
358+
};
359+
360+
static const struct a6xx_registers a7xx_gbif_reglist =
361+
REGS(a7xx_gbif_registers, 0, 0);
362+
341363
static const u32 a6xx_gmu_gx_registers[] = {
342364
/* GMU GX */
343365
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
@@ -384,14 +406,17 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = {
384406
};
385407

386408
static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
409+
static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);
387410

388-
static struct a6xx_indexed_registers {
411+
struct a6xx_indexed_registers {
389412
const char *name;
390413
u32 addr;
391414
u32 data;
392415
u32 count;
393416
u32 (*count_fn)(struct msm_gpu *gpu);
394-
} a6xx_indexed_reglist[] = {
417+
};
418+
419+
static struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
395420
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
396421
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
397422
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
@@ -402,11 +427,43 @@ static struct a6xx_indexed_registers {
402427
REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
403428
};
404429

430+
static struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
431+
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
432+
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
433+
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
434+
REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
435+
{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
436+
REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
437+
{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
438+
REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL },
439+
{ "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
440+
REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL },
441+
{ "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
442+
REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL },
443+
{ "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
444+
REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL },
445+
{ "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
446+
REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL },
447+
{ "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
448+
REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL },
449+
{ "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
450+
REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL },
451+
{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
452+
REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },
453+
};
454+
405455
static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
406456
"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
407457
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
408458
};
409459

460+
static struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
461+
{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
462+
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },
463+
{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
464+
REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL },
465+
};
466+
410467
#define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }
411468

412469
static const struct a6xx_debugbus_block {

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