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torvaldstorvalds
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Merge tag 'drm-fixes-2023-06-02' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Quiet enough week, though the misc fixes tree didn't get to me when I was sending this, so maybe it'll be a bit bigger next week, just one i915 fix and some scattered amdgpu fixes: amdgpu: - Fix mclk and fclk output ordering on some APUs - Fix display regression with 5K VRR - VCN, JPEG spurious interrupt warning fixes - Fix SI DPM on some ARM64 platforms - Fix missing TMZ enablement on GC 11.0.1 i915: - Fix for OA reporting to allow detecting non-power-of-two reports" * tag 'drm-fixes-2023-06-02' of git://anongit.freedesktop.org/drm/drm: drm/i915/perf: Clear out entire reports after reading if not power of 2 size drm/amdgpu: enable tmz by default for GC 11.0.1 drm/amd/pm: resolve reboot exception for si oland drm/amdgpu: add RAS POISON interrupt funcs for jpeg_v4_0 drm/amdgpu: add RAS POISON interrupt funcs for jpeg_v2_6 drm/amdgpu: separate ras irq from jpeg instance irq for UVD_POISON drm/amdgpu: add RAS POISON interrupt funcs for vcn_v4_0 drm/amdgpu: add RAS POISON interrupt funcs for vcn_v2_6 drm/amdgpu: separate ras irq from vcn instance irq for UVD_POISON Revert "drm/amd/display: Do not set drr on pipe commit" Revert "drm/amd/display: Block optimize on consecutive FAMS enables" drm/amd/pm: reverse mclk and fclk clocks levels for renoir drm/amd/pm: reverse mclk and fclk clocks levels for vangogh drm/amd/pm: reverse mclk and fclk clocks levels for yellow carp drm/amd/pm: reverse mclk clocks levels for SMU v13.0.5 drm/amd/pm: reverse mclk and fclk clocks levels for SMU v13.0.4
2 parents 1419c3b + b6ccf21 commit e99a746

18 files changed

Lines changed: 184 additions & 106 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -593,6 +593,8 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
593593
case IP_VERSION(9, 3, 0):
594594
/* GC 10.3.7 */
595595
case IP_VERSION(10, 3, 7):
596+
/* GC 11.0.1 */
597+
case IP_VERSION(11, 0, 1):
596598
if (amdgpu_tmz == 0) {
597599
adev->gmc.tmz_enabled = false;
598600
dev_info(adev->dev,
@@ -616,7 +618,6 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
616618
case IP_VERSION(10, 3, 1):
617619
/* YELLOW_CARP*/
618620
case IP_VERSION(10, 3, 3):
619-
case IP_VERSION(11, 0, 1):
620621
case IP_VERSION(11, 0, 4):
621622
/* Don't enable it by default yet.
622623
*/

‎drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c‎

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -241,6 +241,31 @@ int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
241241
return 0;
242242
}
243243

244+
int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
245+
{
246+
int r, i;
247+
248+
r = amdgpu_ras_block_late_init(adev, ras_block);
249+
if (r)
250+
return r;
251+
252+
if (amdgpu_ras_is_supported(adev, ras_block->block)) {
253+
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
254+
if (adev->jpeg.harvest_config & (1 << i))
255+
continue;
256+
257+
r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
258+
if (r)
259+
goto late_fini;
260+
}
261+
}
262+
return 0;
263+
264+
late_fini:
265+
amdgpu_ras_block_late_fini(adev, ras_block);
266+
return r;
267+
}
268+
244269
int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
245270
{
246271
int err;
@@ -262,7 +287,7 @@ int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
262287
adev->jpeg.ras_if = &ras->ras_block.ras_comm;
263288

264289
if (!ras->ras_block.ras_late_init)
265-
ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
290+
ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init;
266291

267292
return 0;
268293
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ struct amdgpu_jpeg_reg{
3838
struct amdgpu_jpeg_inst {
3939
struct amdgpu_ring ring_dec;
4040
struct amdgpu_irq_src irq;
41+
struct amdgpu_irq_src ras_poison_irq;
4142
struct amdgpu_jpeg_reg external;
4243
};
4344

@@ -72,6 +73,8 @@ int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
7273
int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
7374
struct amdgpu_irq_src *source,
7475
struct amdgpu_iv_entry *entry);
76+
int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev,
77+
struct ras_common_if *ras_block);
7578
int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);
7679

7780
#endif /*__AMDGPU_JPEG_H__*/

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c‎

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1181,6 +1181,31 @@ int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
11811181
return 0;
11821182
}
11831183

1184+
int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
1185+
{
1186+
int r, i;
1187+
1188+
r = amdgpu_ras_block_late_init(adev, ras_block);
1189+
if (r)
1190+
return r;
1191+
1192+
if (amdgpu_ras_is_supported(adev, ras_block->block)) {
1193+
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1194+
if (adev->vcn.harvest_config & (1 << i))
1195+
continue;
1196+
1197+
r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
1198+
if (r)
1199+
goto late_fini;
1200+
}
1201+
}
1202+
return 0;
1203+
1204+
late_fini:
1205+
amdgpu_ras_block_late_fini(adev, ras_block);
1206+
return r;
1207+
}
1208+
11841209
int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
11851210
{
11861211
int err;
@@ -1202,7 +1227,7 @@ int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
12021227
adev->vcn.ras_if = &ras->ras_block.ras_comm;
12031228

12041229
if (!ras->ras_block.ras_late_init)
1205-
ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
1230+
ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init;
12061231

12071232
return 0;
12081233
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -234,6 +234,7 @@ struct amdgpu_vcn_inst {
234234
struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
235235
atomic_t sched_score;
236236
struct amdgpu_irq_src irq;
237+
struct amdgpu_irq_src ras_poison_irq;
237238
struct amdgpu_vcn_reg external;
238239
struct amdgpu_bo *dpg_sram_bo;
239240
struct dpg_pause_state pause_state;
@@ -400,6 +401,8 @@ void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
400401
int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
401402
struct amdgpu_irq_src *source,
402403
struct amdgpu_iv_entry *entry);
404+
int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev,
405+
struct ras_common_if *ras_block);
403406
int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);
404407

405408
#endif

‎drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c‎

Lines changed: 22 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -102,13 +102,13 @@ static int jpeg_v2_5_sw_init(void *handle)
102102

103103
/* JPEG DJPEG POISON EVENT */
104104
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
105-
VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq);
105+
VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq);
106106
if (r)
107107
return r;
108108

109109
/* JPEG EJPEG POISON EVENT */
110110
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
111-
VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq);
111+
VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq);
112112
if (r)
113113
return r;
114114
}
@@ -221,6 +221,9 @@ static int jpeg_v2_5_hw_fini(void *handle)
221221
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
222222
RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
223223
jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
224+
225+
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
226+
amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
224227
}
225228

226229
return 0;
@@ -569,6 +572,14 @@ static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
569572
return 0;
570573
}
571574

575+
static int jpeg_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev,
576+
struct amdgpu_irq_src *source,
577+
unsigned int type,
578+
enum amdgpu_interrupt_state state)
579+
{
580+
return 0;
581+
}
582+
572583
static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
573584
struct amdgpu_irq_src *source,
574585
struct amdgpu_iv_entry *entry)
@@ -593,10 +604,6 @@ static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
593604
case VCN_2_0__SRCID__JPEG_DECODE:
594605
amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec);
595606
break;
596-
case VCN_2_6__SRCID_DJPEG0_POISON:
597-
case VCN_2_6__SRCID_EJPEG0_POISON:
598-
amdgpu_jpeg_process_poison_irq(adev, source, entry);
599-
break;
600607
default:
601608
DRM_ERROR("Unhandled interrupt: %d %d\n",
602609
entry->src_id, entry->src_data[0]);
@@ -725,6 +732,11 @@ static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
725732
.process = jpeg_v2_5_process_interrupt,
726733
};
727734

735+
static const struct amdgpu_irq_src_funcs jpeg_v2_6_ras_irq_funcs = {
736+
.set = jpeg_v2_6_set_ras_interrupt_state,
737+
.process = amdgpu_jpeg_process_poison_irq,
738+
};
739+
728740
static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
729741
{
730742
int i;
@@ -735,6 +747,9 @@ static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
735747

736748
adev->jpeg.inst[i].irq.num_types = 1;
737749
adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
750+
751+
adev->jpeg.inst[i].ras_poison_irq.num_types = 1;
752+
adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs;
738753
}
739754
}
740755

@@ -800,6 +815,7 @@ const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = {
800815
static struct amdgpu_jpeg_ras jpeg_v2_6_ras = {
801816
.ras_block = {
802817
.hw_ops = &jpeg_v2_6_ras_hw_ops,
818+
.ras_late_init = amdgpu_jpeg_ras_late_init,
803819
},
804820
};
805821

‎drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c‎

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -87,13 +87,13 @@ static int jpeg_v4_0_sw_init(void *handle)
8787

8888
/* JPEG DJPEG POISON EVENT */
8989
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
90-
VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->irq);
90+
VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
9191
if (r)
9292
return r;
9393

9494
/* JPEG EJPEG POISON EVENT */
9595
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
96-
VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->irq);
96+
VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
9797
if (r)
9898
return r;
9999

@@ -202,7 +202,8 @@ static int jpeg_v4_0_hw_fini(void *handle)
202202
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
203203
jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
204204
}
205-
amdgpu_irq_put(adev, &adev->jpeg.inst->irq, 0);
205+
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
206+
amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
206207

207208
return 0;
208209
}
@@ -670,6 +671,14 @@ static int jpeg_v4_0_set_interrupt_state(struct amdgpu_device *adev,
670671
return 0;
671672
}
672673

674+
static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
675+
struct amdgpu_irq_src *source,
676+
unsigned int type,
677+
enum amdgpu_interrupt_state state)
678+
{
679+
return 0;
680+
}
681+
673682
static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,
674683
struct amdgpu_irq_src *source,
675684
struct amdgpu_iv_entry *entry)
@@ -680,10 +689,6 @@ static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,
680689
case VCN_4_0__SRCID__JPEG_DECODE:
681690
amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
682691
break;
683-
case VCN_4_0__SRCID_DJPEG0_POISON:
684-
case VCN_4_0__SRCID_EJPEG0_POISON:
685-
amdgpu_jpeg_process_poison_irq(adev, source, entry);
686-
break;
687692
default:
688693
DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
689694
entry->src_id, entry->src_data[0]);
@@ -753,10 +758,18 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = {
753758
.process = jpeg_v4_0_process_interrupt,
754759
};
755760

761+
static const struct amdgpu_irq_src_funcs jpeg_v4_0_ras_irq_funcs = {
762+
.set = jpeg_v4_0_set_ras_interrupt_state,
763+
.process = amdgpu_jpeg_process_poison_irq,
764+
};
765+
756766
static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev)
757767
{
758768
adev->jpeg.inst->irq.num_types = 1;
759769
adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;
770+
771+
adev->jpeg.inst->ras_poison_irq.num_types = 1;
772+
adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;
760773
}
761774

762775
const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = {
@@ -811,6 +824,7 @@ const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = {
811824
static struct amdgpu_jpeg_ras jpeg_v4_0_ras = {
812825
.ras_block = {
813826
.hw_ops = &jpeg_v4_0_ras_hw_ops,
827+
.ras_late_init = amdgpu_jpeg_ras_late_init,
814828
},
815829
};
816830

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c‎

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ static int vcn_v2_5_sw_init(void *handle)
143143

144144
/* VCN POISON TRAP */
145145
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
146-
VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].irq);
146+
VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq);
147147
if (r)
148148
return r;
149149
}
@@ -354,6 +354,9 @@ static int vcn_v2_5_hw_fini(void *handle)
354354
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
355355
RREG32_SOC15(VCN, i, mmUVD_STATUS)))
356356
vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
357+
358+
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
359+
amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
357360
}
358361

359362
return 0;
@@ -1807,6 +1810,14 @@ static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
18071810
return 0;
18081811
}
18091812

1813+
static int vcn_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev,
1814+
struct amdgpu_irq_src *source,
1815+
unsigned int type,
1816+
enum amdgpu_interrupt_state state)
1817+
{
1818+
return 0;
1819+
}
1820+
18101821
static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
18111822
struct amdgpu_irq_src *source,
18121823
struct amdgpu_iv_entry *entry)
@@ -1837,9 +1848,6 @@ static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
18371848
case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
18381849
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
18391850
break;
1840-
case VCN_2_6__SRCID_UVD_POISON:
1841-
amdgpu_vcn_process_poison_irq(adev, source, entry);
1842-
break;
18431851
default:
18441852
DRM_ERROR("Unhandled interrupt: %d %d\n",
18451853
entry->src_id, entry->src_data[0]);
@@ -1854,6 +1862,11 @@ static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
18541862
.process = vcn_v2_5_process_interrupt,
18551863
};
18561864

1865+
static const struct amdgpu_irq_src_funcs vcn_v2_6_ras_irq_funcs = {
1866+
.set = vcn_v2_6_set_ras_interrupt_state,
1867+
.process = amdgpu_vcn_process_poison_irq,
1868+
};
1869+
18571870
static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
18581871
{
18591872
int i;
@@ -1863,6 +1876,9 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
18631876
continue;
18641877
adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
18651878
adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
1879+
1880+
adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
1881+
adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs;
18661882
}
18671883
}
18681884

@@ -1965,6 +1981,7 @@ const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = {
19651981
static struct amdgpu_vcn_ras vcn_v2_6_ras = {
19661982
.ras_block = {
19671983
.hw_ops = &vcn_v2_6_ras_hw_ops,
1984+
.ras_late_init = amdgpu_vcn_ras_late_init,
19681985
},
19691986
};
19701987

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