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sumang-mrvldavem330
sumang-mrvl
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davem330
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octeontx2-af: Unlock contexts in the queue context cache in case of fault detection
NDC caches contexts of frequently used queue's (Rx and Tx queues) contexts. Due to a HW errata when NDC detects fault/poision while accessing contexts it could go into an illegal state where a cache line could get locked forever. To makesure all cache lines in NDC are available for optimum performance upon fault/lockerror/posion errors scan through all cache lines in NDC and clear the lock bit. Fixes: 4a3581c ("octeontx2-af: NPA AQ instruction enqueue support") Signed-off-by: Suman Ghosh <sumang@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Sai Krishna <saikrishnag@marvell.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent ce7ca79 commit ea9dd2e

5 files changed

Lines changed: 82 additions & 7 deletions

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‎drivers/net/ethernet/marvell/octeontx2/af/rvu.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -884,6 +884,9 @@ int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
884884
int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
885885
int rvu_cpt_init(struct rvu *rvu);
886886

887+
#define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
888+
#define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
889+
887890
/* CN10K RVU */
888891
int rvu_set_channels_base(struct rvu *rvu);
889892
void rvu_program_channels(struct rvu *rvu);
@@ -902,6 +905,8 @@ static inline void rvu_dbg_init(struct rvu *rvu) {}
902905
static inline void rvu_dbg_exit(struct rvu *rvu) {}
903906
#endif
904907

908+
int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
909+
905910
/* RVU Switch */
906911
void rvu_switch_enable(struct rvu *rvu);
907912
void rvu_switch_disable(struct rvu *rvu);

‎drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -198,9 +198,6 @@ enum cpt_eng_type {
198198
CPT_IE_TYPE = 3,
199199
};
200200

201-
#define NDC_MAX_BANK(rvu, blk_addr) (rvu_read64(rvu, \
202-
blk_addr, NDC_AF_CONST) & 0xFF)
203-
204201
#define rvu_dbg_NULL NULL
205202
#define rvu_dbg_open_NULL NULL
206203

@@ -1448,6 +1445,7 @@ static int ndc_blk_hits_miss_stats(struct seq_file *s, int idx, int blk_addr)
14481445
struct nix_hw *nix_hw;
14491446
struct rvu *rvu;
14501447
int bank, max_bank;
1448+
u64 ndc_af_const;
14511449

14521450
if (blk_addr == BLKADDR_NDC_NPA0) {
14531451
rvu = s->private;
@@ -1456,7 +1454,8 @@ static int ndc_blk_hits_miss_stats(struct seq_file *s, int idx, int blk_addr)
14561454
rvu = nix_hw->rvu;
14571455
}
14581456

1459-
max_bank = NDC_MAX_BANK(rvu, blk_addr);
1457+
ndc_af_const = rvu_read64(rvu, blk_addr, NDC_AF_CONST);
1458+
max_bank = FIELD_GET(NDC_AF_BANK_MASK, ndc_af_const);
14601459
for (bank = 0; bank < max_bank; bank++) {
14611460
seq_printf(s, "BANK:%d\n", bank);
14621461
seq_printf(s, "\tHits:\t%lld\n",

‎drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -790,6 +790,7 @@ static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block,
790790
struct nix_aq_res_s *result;
791791
int timeout = 1000;
792792
u64 reg, head;
793+
int ret;
793794

794795
result = (struct nix_aq_res_s *)aq->res->base;
795796

@@ -813,9 +814,22 @@ static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block,
813814
return -EBUSY;
814815
}
815816

816-
if (result->compcode != NIX_AQ_COMP_GOOD)
817+
if (result->compcode != NIX_AQ_COMP_GOOD) {
817818
/* TODO: Replace this with some error code */
819+
if (result->compcode == NIX_AQ_COMP_CTX_FAULT ||
820+
result->compcode == NIX_AQ_COMP_LOCKERR ||
821+
result->compcode == NIX_AQ_COMP_CTX_POISON) {
822+
ret = rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX0_RX);
823+
ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX0_TX);
824+
ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX1_RX);
825+
ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX1_TX);
826+
if (ret)
827+
dev_err(rvu->dev,
828+
"%s: Not able to unlock cachelines\n", __func__);
829+
}
830+
818831
return -EBUSY;
832+
}
819833

820834
return 0;
821835
}

‎drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c‎

Lines changed: 56 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* Copyright (C) 2018 Marvell.
55
*
66
*/
7-
7+
#include <linux/bitfield.h>
88
#include <linux/module.h>
99
#include <linux/pci.h>
1010

@@ -42,9 +42,18 @@ static int npa_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block,
4242
return -EBUSY;
4343
}
4444

45-
if (result->compcode != NPA_AQ_COMP_GOOD)
45+
if (result->compcode != NPA_AQ_COMP_GOOD) {
4646
/* TODO: Replace this with some error code */
47+
if (result->compcode == NPA_AQ_COMP_CTX_FAULT ||
48+
result->compcode == NPA_AQ_COMP_LOCKERR ||
49+
result->compcode == NPA_AQ_COMP_CTX_POISON) {
50+
if (rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NPA0))
51+
dev_err(rvu->dev,
52+
"%s: Not able to unlock cachelines\n", __func__);
53+
}
54+
4755
return -EBUSY;
56+
}
4857

4958
return 0;
5059
}
@@ -545,3 +554,48 @@ void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf)
545554

546555
npa_ctx_free(rvu, pfvf);
547556
}
557+
558+
/* Due to an Hardware errata, in some corner cases, AQ context lock
559+
* operations can result in a NDC way getting into an illegal state
560+
* of not valid but locked.
561+
*
562+
* This API solves the problem by clearing the lock bit of the NDC block.
563+
* The operation needs to be done for each line of all the NDC banks.
564+
*/
565+
int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr)
566+
{
567+
int bank, max_bank, line, max_line, err;
568+
u64 reg, ndc_af_const;
569+
570+
/* Set the ENABLE bit(63) to '0' */
571+
reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL);
572+
rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & GENMASK_ULL(62, 0));
573+
574+
/* Poll until the BUSY bits(47:32) are set to '0' */
575+
err = rvu_poll_reg(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, GENMASK_ULL(47, 32), true);
576+
if (err) {
577+
dev_err(rvu->dev, "Timed out while polling for NDC CAM busy bits.\n");
578+
return err;
579+
}
580+
581+
ndc_af_const = rvu_read64(rvu, blkaddr, NDC_AF_CONST);
582+
max_bank = FIELD_GET(NDC_AF_BANK_MASK, ndc_af_const);
583+
max_line = FIELD_GET(NDC_AF_BANK_LINE_MASK, ndc_af_const);
584+
for (bank = 0; bank < max_bank; bank++) {
585+
for (line = 0; line < max_line; line++) {
586+
/* Check if 'cache line valid bit(63)' is not set
587+
* but 'cache line lock bit(60)' is set and on
588+
* success, reset the lock bit(60).
589+
*/
590+
reg = rvu_read64(rvu, blkaddr,
591+
NDC_AF_BANKX_LINEX_METADATA(bank, line));
592+
if (!(reg & BIT_ULL(63)) && (reg & BIT_ULL(60))) {
593+
rvu_write64(rvu, blkaddr,
594+
NDC_AF_BANKX_LINEX_METADATA(bank, line),
595+
reg & ~BIT_ULL(60));
596+
}
597+
}
598+
}
599+
600+
return 0;
601+
}

‎drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -694,6 +694,7 @@
694694
#define NDC_AF_INTR_ENA_W1S (0x00068)
695695
#define NDC_AF_INTR_ENA_W1C (0x00070)
696696
#define NDC_AF_ACTIVE_PC (0x00078)
697+
#define NDC_AF_CAMS_RD_INTERVAL (0x00080)
697698
#define NDC_AF_BP_TEST_ENABLE (0x001F8)
698699
#define NDC_AF_BP_TEST(a) (0x00200 | (a) << 3)
699700
#define NDC_AF_BLK_RST (0x002F0)
@@ -709,6 +710,8 @@
709710
(0x00F00 | (a) << 5 | (b) << 4)
710711
#define NDC_AF_BANKX_HIT_PC(a) (0x01000 | (a) << 3)
711712
#define NDC_AF_BANKX_MISS_PC(a) (0x01100 | (a) << 3)
713+
#define NDC_AF_BANKX_LINEX_METADATA(a, b) \
714+
(0x10000 | (a) << 12 | (b) << 3)
712715

713716
/* LBK */
714717
#define LBK_CONST (0x10ull)

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