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Merge tag 'intel-pinctrl-v6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.20-1 * Add Nova Lake to the list of supported platforms by platform driver * Update Kconfig help text to clarify which drivers supports which platforms * Convert more Intel pin control drivers to use intel_gpio_add_pin_ranges() Signed-off-by: Linus Walleij <linusw@kernel.org>
2 parents a4cf8f9 + fc32c57 commit ebd2f48

3 files changed

Lines changed: 50 additions & 40 deletions

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‎drivers/pinctrl/intel/Kconfig‎

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -45,14 +45,18 @@ config PINCTRL_INTEL_PLATFORM
4545
of Intel PCH pins and using them as GPIOs. Currently the following
4646
Intel SoCs / platforms require this to be functional:
4747
- Lunar Lake
48+
- Nova Lake
4849
- Panther Lake
4950

5051
config PINCTRL_ALDERLAKE
5152
tristate "Intel Alder Lake pinctrl and GPIO driver"
5253
select PINCTRL_INTEL
5354
help
5455
This pinctrl driver provides an interface that allows configuring
55-
of Intel Alder Lake PCH pins and using them as GPIOs.
56+
PCH pins of the following platforms and using them as GPIOs:
57+
- Alder Lake HX, N, and S
58+
- Raptor Lake HX, E, and S
59+
- Twin Lake
5660

5761
config PINCTRL_BROXTON
5862
tristate "Intel Broxton pinctrl and GPIO driver"
@@ -136,15 +140,17 @@ config PINCTRL_METEORLAKE
136140
select PINCTRL_INTEL
137141
help
138142
This pinctrl driver provides an interface that allows configuring
139-
of Intel Meteor Lake pins and using them as GPIOs.
143+
SoC pins of the following platforms and using them as GPIOs:
144+
- Arrow Lake (all variants)
145+
- Meteor Lake (all variants)
140146

141147
config PINCTRL_METEORPOINT
142148
tristate "Intel Meteor Point pinctrl and GPIO driver"
143149
select PINCTRL_INTEL
144150
help
145-
Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver
146-
provides an interface that allows configuring of PCH pins and
147-
using them as GPIOs.
151+
This pinctrl driver provides an interface that allows configuring
152+
PCH pins of the following platforms and using them as GPIOs:
153+
- Arrow Lake HX and S
148154

149155
config PINCTRL_SUNRISEPOINT
150156
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
@@ -159,7 +165,11 @@ config PINCTRL_TIGERLAKE
159165
select PINCTRL_INTEL
160166
help
161167
This pinctrl driver provides an interface that allows configuring
162-
of Intel Tiger Lake PCH pins and using them as GPIOs.
168+
PCH pins of the following platforms and using them as GPIOs:
169+
- Alder Lake H, P, PS, and U
170+
- Raptor Lake H, P, PS, PX, and U
171+
- Rocket Lake S
172+
- Tiger Lake (all variants)
163173

164174
source "drivers/pinctrl/intel/Kconfig.tng"
165175
endmenu

‎drivers/pinctrl/intel/pinctrl-baytrail.c‎

Lines changed: 23 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -101,10 +101,12 @@ struct intel_pad_context {
101101
u32 val;
102102
};
103103

104-
#define COMMUNITY(p, n, map) \
104+
#define BYT_COMMUNITY(p, n, g, map) \
105105
{ \
106106
.pin_base = (p), \
107107
.npins = (n), \
108+
.gpps = (g), \
109+
.ngpps = ARRAY_SIZE(g), \
108110
.pad_map = (map),\
109111
}
110112

@@ -360,8 +362,15 @@ static const struct intel_function byt_score_functions[] = {
360362
FUNCTION("gpio", byt_score_gpio_groups),
361363
};
362364

365+
static const struct intel_padgroup byt_score_gpps[] = {
366+
INTEL_GPP(0, 0, 31, 0),
367+
INTEL_GPP(1, 32, 63, 32),
368+
INTEL_GPP(2, 64, 95, 64),
369+
INTEL_GPP(3, 96, 101, 96),
370+
};
371+
363372
static const struct intel_community byt_score_communities[] = {
364-
COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
373+
BYT_COMMUNITY(0, 102, byt_score_gpps, byt_score_pins_map),
365374
};
366375

367376
static const struct intel_pinctrl_soc_data byt_score_soc_data = {
@@ -483,8 +492,13 @@ static const struct intel_function byt_sus_functions[] = {
483492
FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
484493
};
485494

495+
static const struct intel_padgroup byt_sus_gpps[] = {
496+
INTEL_GPP(0, 0, 31, 0),
497+
INTEL_GPP(1, 32, 43, 32),
498+
};
499+
486500
static const struct intel_community byt_sus_communities[] = {
487-
COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
501+
BYT_COMMUNITY(0, 44, byt_sus_gpps, byt_sus_pins_map),
488502
};
489503

490504
static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
@@ -536,8 +550,12 @@ static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
536550
3, 6, 10, 13, 2, 5, 9, 7,
537551
};
538552

553+
static const struct intel_padgroup byt_ncore_gpps[] = {
554+
INTEL_GPP(0, 0, 27, 0),
555+
};
556+
539557
static const struct intel_community byt_ncore_communities[] = {
540-
COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
558+
BYT_COMMUNITY(0, 28, byt_ncore_gpps, byt_ncore_pins_map),
541559
};
542560

543561
static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
@@ -1490,19 +1508,6 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
14901508
return 0;
14911509
}
14921510

1493-
static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1494-
{
1495-
struct intel_pinctrl *vg = gpiochip_get_data(chip);
1496-
struct device *dev = vg->dev;
1497-
int ret;
1498-
1499-
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1500-
if (ret)
1501-
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
1502-
1503-
return 0;
1504-
}
1505-
15061511
static int byt_gpio_probe(struct intel_pinctrl *vg)
15071512
{
15081513
struct platform_device *pdev = to_platform_device(vg->dev);
@@ -1515,7 +1520,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
15151520
gc->label = dev_name(vg->dev);
15161521
gc->base = -1;
15171522
gc->can_sleep = false;
1518-
gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1523+
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
15191524
gc->parent = vg->dev;
15201525
gc->ngpio = vg->soc->npins;
15211526

‎drivers/pinctrl/intel/pinctrl-lynxpoint.c‎

Lines changed: 11 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -29,10 +29,12 @@
2929

3030
#include "pinctrl-intel.h"
3131

32-
#define COMMUNITY(p, n) \
32+
#define LPTLP_COMMUNITY(p, n, g) \
3333
{ \
3434
.pin_base = (p), \
3535
.npins = (n), \
36+
.gpps = (g), \
37+
.ngpps = ARRAY_SIZE(g), \
3638
}
3739

3840
static const struct pinctrl_pin_desc lptlp_pins[] = {
@@ -133,8 +135,14 @@ static const struct pinctrl_pin_desc lptlp_pins[] = {
133135
PINCTRL_PIN(94, "GP94_UART0_CTSB"),
134136
};
135137

138+
static const struct intel_padgroup lptlp_gpps[] = {
139+
INTEL_GPP(0, 0, 31, 0),
140+
INTEL_GPP(1, 32, 63, 32),
141+
INTEL_GPP(2, 64, 94, 64),
142+
};
143+
136144
static const struct intel_community lptlp_communities[] = {
137-
COMMUNITY(0, 95),
145+
LPTLP_COMMUNITY(0, 95, lptlp_gpps),
138146
};
139147

140148
static const struct intel_pinctrl_soc_data lptlp_soc_data = {
@@ -692,19 +700,6 @@ static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
692700
return 0;
693701
}
694702

695-
static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
696-
{
697-
struct intel_pinctrl *lg = gpiochip_get_data(chip);
698-
struct device *dev = lg->dev;
699-
int ret;
700-
701-
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
702-
if (ret)
703-
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
704-
705-
return 0;
706-
}
707-
708703
static int lp_gpio_probe(struct platform_device *pdev)
709704
{
710705
const struct intel_pinctrl_soc_data *soc;
@@ -777,7 +772,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
777772
gc->base = -1;
778773
gc->ngpio = LP_NUM_GPIO;
779774
gc->can_sleep = false;
780-
gc->add_pin_ranges = lp_gpio_add_pin_ranges;
775+
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
781776
gc->parent = dev;
782777

783778
/* set up interrupts */

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