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ychuang3arndb
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clk: nuvoton: Update all constant hex values to lowercase
The constant hex values used to define register offsets were written in uppercase. This patch update all these constant hex values to be lowercase. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1 parent a5e3f37 commit ebd617b

1 file changed

Lines changed: 16 additions & 16 deletions

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drivers/clk/nuvoton/clk-ma35d1.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -22,19 +22,19 @@ static DEFINE_SPINLOCK(ma35d1_lock);
2222
#define REG_CLK_PWRCTL 0x00
2323
#define REG_CLK_SYSCLK0 0x04
2424
#define REG_CLK_SYSCLK1 0x08
25-
#define REG_CLK_APBCLK0 0x0C
25+
#define REG_CLK_APBCLK0 0x0c
2626
#define REG_CLK_APBCLK1 0x10
2727
#define REG_CLK_APBCLK2 0x14
2828
#define REG_CLK_CLKSEL0 0x18
29-
#define REG_CLK_CLKSEL1 0x1C
29+
#define REG_CLK_CLKSEL1 0x1c
3030
#define REG_CLK_CLKSEL2 0x20
3131
#define REG_CLK_CLKSEL3 0x24
3232
#define REG_CLK_CLKSEL4 0x28
33-
#define REG_CLK_CLKDIV0 0x2C
33+
#define REG_CLK_CLKDIV0 0x2c
3434
#define REG_CLK_CLKDIV1 0x30
3535
#define REG_CLK_CLKDIV2 0x34
3636
#define REG_CLK_CLKDIV3 0x38
37-
#define REG_CLK_CLKDIV4 0x3C
37+
#define REG_CLK_CLKDIV4 0x3c
3838
#define REG_CLK_CLKOCTL 0x40
3939
#define REG_CLK_STATUS 0x50
4040
#define REG_CLK_PLL0CTL0 0x60
@@ -44,18 +44,18 @@ static DEFINE_SPINLOCK(ma35d1_lock);
4444
#define REG_CLK_PLL3CTL0 0x90
4545
#define REG_CLK_PLL3CTL1 0x94
4646
#define REG_CLK_PLL3CTL2 0x98
47-
#define REG_CLK_PLL4CTL0 0xA0
48-
#define REG_CLK_PLL4CTL1 0xA4
49-
#define REG_CLK_PLL4CTL2 0xA8
50-
#define REG_CLK_PLL5CTL0 0xB0
51-
#define REG_CLK_PLL5CTL1 0xB4
52-
#define REG_CLK_PLL5CTL2 0xB8
53-
#define REG_CLK_CLKDCTL 0xC0
54-
#define REG_CLK_CLKDSTS 0xC4
55-
#define REG_CLK_CDUPB 0xC8
56-
#define REG_CLK_CDLOWB 0xCC
57-
#define REG_CLK_CKFLTRCTL 0xD0
58-
#define REG_CLK_TESTCLK 0xF0
47+
#define REG_CLK_PLL4CTL0 0xa0
48+
#define REG_CLK_PLL4CTL1 0xa4
49+
#define REG_CLK_PLL4CTL2 0xa8
50+
#define REG_CLK_PLL5CTL0 0xb0
51+
#define REG_CLK_PLL5CTL1 0xb4
52+
#define REG_CLK_PLL5CTL2 0xb8
53+
#define REG_CLK_CLKDCTL 0xc0
54+
#define REG_CLK_CLKDSTS 0xc4
55+
#define REG_CLK_CDUPB 0xc8
56+
#define REG_CLK_CDLOWB 0xcc
57+
#define REG_CLK_CKFLTRCTL 0xd0
58+
#define REG_CLK_TESTCLK 0xf0
5959
#define REG_CLK_PLLCTL 0x40
6060

6161
#define PLL_MODE_INT 0

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