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geertubroonie
geertu
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spi: sh-msiof: Move register definitions to <linux/spi/sh_msiof.h>
Move the MSIOF register and register bit definitions from the MSIOF SPI driver to the existing header file <linux/spi/sh_msiof.h>, so they can be shared with the MSIOF I2S driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/066d1086973eb309006258484e9fe8138807e565.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
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Lines changed: 125 additions & 124 deletions

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‎drivers/spi/spi-sh-msiof.c‎

Lines changed: 0 additions & 124 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
77
* Copyright (C) 2014-2017 Glider bvba
88
*/
99

10-
#include <linux/bitfield.h>
1110
#include <linux/bitmap.h>
1211
#include <linux/clk.h>
1312
#include <linux/completion.h>
@@ -64,129 +63,6 @@ struct sh_msiof_spi_priv {
6463

6564
#define MAX_SS 3 /* Maximum number of native chip selects */
6665

67-
#define SITMDR1 0x00 /* Transmit Mode Register 1 */
68-
#define SITMDR2 0x04 /* Transmit Mode Register 2 */
69-
#define SITMDR3 0x08 /* Transmit Mode Register 3 */
70-
#define SIRMDR1 0x10 /* Receive Mode Register 1 */
71-
#define SIRMDR2 0x14 /* Receive Mode Register 2 */
72-
#define SIRMDR3 0x18 /* Receive Mode Register 3 */
73-
#define SITSCR 0x20 /* Transmit Clock Select Register */
74-
#define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
75-
#define SICTR 0x28 /* Control Register */
76-
#define SIFCTR 0x30 /* FIFO Control Register */
77-
#define SISTR 0x40 /* Status Register */
78-
#define SIIER 0x44 /* Interrupt Enable Register */
79-
#define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
80-
#define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
81-
#define SITFDR 0x50 /* Transmit FIFO Data Register */
82-
#define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
83-
#define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
84-
#define SIRFDR 0x60 /* Receive FIFO Data Register */
85-
86-
/* SITMDR1 and SIRMDR1 */
87-
#define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
88-
#define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
89-
#define SIMDR1_SYNCMD_PULSE 0U /* Frame start sync pulse */
90-
#define SIMDR1_SYNCMD_SPI 2U /* Level mode/SPI */
91-
#define SIMDR1_SYNCMD_LR 3U /* L/R mode */
92-
#define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
93-
#define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */
94-
#define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */
95-
#define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */
96-
#define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
97-
#define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
98-
/* SITMDR1 */
99-
#define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
100-
#define SITMDR1_SYNCCH GENMASK(27, 26) /* Sync Signal Channel Select */
101-
/* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
102-
103-
/* SITMDR2 and SIRMDR2 */
104-
#define SIMDR2_GRP GENMASK(31, 30) /* Group Count */
105-
#define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
106-
#define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
107-
#define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */
108-
109-
/* SITMDR3 and SIRMDR3 */
110-
#define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */
111-
#define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
112-
113-
/* SITSCR and SIRSCR */
114-
#define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */
115-
#define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
116-
117-
/* SICTR */
118-
#define SICTR_TSCKIZ GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
119-
#define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
120-
#define SICTR_TSCKIZ_POL BIT(30) /* Transmit Clock Polarity */
121-
#define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */
122-
#define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
123-
#define SICTR_RSCKIZ_POL BIT(28) /* Receive Clock Polarity */
124-
#define SICTR_TEDG BIT(27) /* Transmit Timing (1 = falling edge) */
125-
#define SICTR_REDG BIT(26) /* Receive Timing (1 = falling edge) */
126-
#define SICTR_TXDIZ GENMASK(23, 22) /* Pin Output When TX is Disabled */
127-
#define SICTR_TXDIZ_LOW 0U /* 0 */
128-
#define SICTR_TXDIZ_HIGH 1U /* 1 */
129-
#define SICTR_TXDIZ_HIZ 2U /* High-impedance */
130-
#define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
131-
#define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
132-
#define SICTR_TXE BIT(9) /* Transmit Enable */
133-
#define SICTR_RXE BIT(8) /* Receive Enable */
134-
#define SICTR_TXRST BIT(1) /* Transmit Reset */
135-
#define SICTR_RXRST BIT(0) /* Receive Reset */
136-
137-
/* SIFCTR */
138-
#define SIFCTR_TFWM GENMASK(31, 29) /* Transmit FIFO Watermark */
139-
#define SIFCTR_TFWM_64 0U /* Transfer Request when 64 empty stages */
140-
#define SIFCTR_TFWM_32 1U /* Transfer Request when 32 empty stages */
141-
#define SIFCTR_TFWM_24 2U /* Transfer Request when 24 empty stages */
142-
#define SIFCTR_TFWM_16 3U /* Transfer Request when 16 empty stages */
143-
#define SIFCTR_TFWM_12 4U /* Transfer Request when 12 empty stages */
144-
#define SIFCTR_TFWM_8 5U /* Transfer Request when 8 empty stages */
145-
#define SIFCTR_TFWM_4 6U /* Transfer Request when 4 empty stages */
146-
#define SIFCTR_TFWM_1 7U /* Transfer Request when 1 empty stage */
147-
#define SIFCTR_TFUA GENMASK(28, 20) /* Transmit FIFO Usable Area */
148-
#define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */
149-
#define SIFCTR_RFWM_1 0U /* Transfer Request when 1 valid stages */
150-
#define SIFCTR_RFWM_4 1U /* Transfer Request when 4 valid stages */
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#define SIFCTR_RFWM_8 2U /* Transfer Request when 8 valid stages */
152-
#define SIFCTR_RFWM_16 3U /* Transfer Request when 16 valid stages */
153-
#define SIFCTR_RFWM_32 4U /* Transfer Request when 32 valid stages */
154-
#define SIFCTR_RFWM_64 5U /* Transfer Request when 64 valid stages */
155-
#define SIFCTR_RFWM_128 6U /* Transfer Request when 128 valid stages */
156-
#define SIFCTR_RFWM_256 7U /* Transfer Request when 256 valid stages */
157-
#define SIFCTR_RFUA GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
158-
159-
/* SISTR */
160-
#define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */
161-
#define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */
162-
#define SISTR_TEOF BIT(23) /* Frame Transmission End */
163-
#define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
164-
#define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */
165-
#define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */
166-
#define SISTR_RFFUL BIT(13) /* Receive FIFO Full */
167-
#define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */
168-
#define SISTR_REOF BIT(7) /* Frame Reception End */
169-
#define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
170-
#define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */
171-
#define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */
172-
173-
/* SIIER */
174-
#define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
175-
#define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
176-
#define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
177-
#define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */
178-
#define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
179-
#define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
180-
#define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
181-
#define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
182-
#define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */
183-
#define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
184-
#define SIIER_REOFE BIT(7) /* Frame Reception End Enable */
185-
#define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
186-
#define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
187-
#define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
188-
189-
19066
static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
19167
{
19268
switch (reg_offs) {

‎include/linux/spi/sh_msiof.h‎

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,131 @@
22
#ifndef __SPI_SH_MSIOF_H__
33
#define __SPI_SH_MSIOF_H__
44

5+
#include <linux/bitfield.h>
6+
#include <linux/bits.h>
7+
8+
#define SITMDR1 0x00 /* Transmit Mode Register 1 */
9+
#define SITMDR2 0x04 /* Transmit Mode Register 2 */
10+
#define SITMDR3 0x08 /* Transmit Mode Register 3 */
11+
#define SIRMDR1 0x10 /* Receive Mode Register 1 */
12+
#define SIRMDR2 0x14 /* Receive Mode Register 2 */
13+
#define SIRMDR3 0x18 /* Receive Mode Register 3 */
14+
#define SITSCR 0x20 /* Transmit Clock Select Register */
15+
#define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
16+
#define SICTR 0x28 /* Control Register */
17+
#define SIFCTR 0x30 /* FIFO Control Register */
18+
#define SISTR 0x40 /* Status Register */
19+
#define SIIER 0x44 /* Interrupt Enable Register */
20+
#define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
21+
#define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
22+
#define SITFDR 0x50 /* Transmit FIFO Data Register */
23+
#define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
24+
#define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
25+
#define SIRFDR 0x60 /* Receive FIFO Data Register */
26+
27+
/* SITMDR1 and SIRMDR1 */
28+
#define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
29+
#define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
30+
#define SIMDR1_SYNCMD_PULSE 0U /* Frame start sync pulse */
31+
#define SIMDR1_SYNCMD_SPI 2U /* Level mode/SPI */
32+
#define SIMDR1_SYNCMD_LR 3U /* L/R mode */
33+
#define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
34+
#define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */
35+
#define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */
36+
#define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */
37+
#define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
38+
#define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
39+
/* SITMDR1 */
40+
#define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
41+
#define SITMDR1_SYNCCH GENMASK(27, 26) /* Sync Signal Channel Select */
42+
/* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
43+
44+
/* SITMDR2 and SIRMDR2 */
45+
#define SIMDR2_GRP GENMASK(31, 30) /* Group Count */
46+
#define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
47+
#define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
48+
#define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */
49+
50+
/* SITMDR3 and SIRMDR3 */
51+
#define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */
52+
#define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
53+
54+
/* SITSCR and SIRSCR */
55+
#define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */
56+
#define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
57+
58+
/* SICTR */
59+
#define SICTR_TSCKIZ GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
60+
#define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
61+
#define SICTR_TSCKIZ_POL BIT(30) /* Transmit Clock Polarity */
62+
#define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */
63+
#define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
64+
#define SICTR_RSCKIZ_POL BIT(28) /* Receive Clock Polarity */
65+
#define SICTR_TEDG BIT(27) /* Transmit Timing (1 = falling edge) */
66+
#define SICTR_REDG BIT(26) /* Receive Timing (1 = falling edge) */
67+
#define SICTR_TXDIZ GENMASK(23, 22) /* Pin Output When TX is Disabled */
68+
#define SICTR_TXDIZ_LOW 0U /* 0 */
69+
#define SICTR_TXDIZ_HIGH 1U /* 1 */
70+
#define SICTR_TXDIZ_HIZ 2U /* High-impedance */
71+
#define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
72+
#define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
73+
#define SICTR_TXE BIT(9) /* Transmit Enable */
74+
#define SICTR_RXE BIT(8) /* Receive Enable */
75+
#define SICTR_TXRST BIT(1) /* Transmit Reset */
76+
#define SICTR_RXRST BIT(0) /* Receive Reset */
77+
78+
/* SIFCTR */
79+
#define SIFCTR_TFWM GENMASK(31, 29) /* Transmit FIFO Watermark */
80+
#define SIFCTR_TFWM_64 0U /* Transfer Request when 64 empty stages */
81+
#define SIFCTR_TFWM_32 1U /* Transfer Request when 32 empty stages */
82+
#define SIFCTR_TFWM_24 2U /* Transfer Request when 24 empty stages */
83+
#define SIFCTR_TFWM_16 3U /* Transfer Request when 16 empty stages */
84+
#define SIFCTR_TFWM_12 4U /* Transfer Request when 12 empty stages */
85+
#define SIFCTR_TFWM_8 5U /* Transfer Request when 8 empty stages */
86+
#define SIFCTR_TFWM_4 6U /* Transfer Request when 4 empty stages */
87+
#define SIFCTR_TFWM_1 7U /* Transfer Request when 1 empty stage */
88+
#define SIFCTR_TFUA GENMASK(28, 20) /* Transmit FIFO Usable Area */
89+
#define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */
90+
#define SIFCTR_RFWM_1 0U /* Transfer Request when 1 valid stages */
91+
#define SIFCTR_RFWM_4 1U /* Transfer Request when 4 valid stages */
92+
#define SIFCTR_RFWM_8 2U /* Transfer Request when 8 valid stages */
93+
#define SIFCTR_RFWM_16 3U /* Transfer Request when 16 valid stages */
94+
#define SIFCTR_RFWM_32 4U /* Transfer Request when 32 valid stages */
95+
#define SIFCTR_RFWM_64 5U /* Transfer Request when 64 valid stages */
96+
#define SIFCTR_RFWM_128 6U /* Transfer Request when 128 valid stages */
97+
#define SIFCTR_RFWM_256 7U /* Transfer Request when 256 valid stages */
98+
#define SIFCTR_RFUA GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
99+
100+
/* SISTR */
101+
#define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */
102+
#define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */
103+
#define SISTR_TEOF BIT(23) /* Frame Transmission End */
104+
#define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
105+
#define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */
106+
#define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */
107+
#define SISTR_RFFUL BIT(13) /* Receive FIFO Full */
108+
#define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */
109+
#define SISTR_REOF BIT(7) /* Frame Reception End */
110+
#define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
111+
#define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */
112+
#define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */
113+
114+
/* SIIER */
115+
#define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
116+
#define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
117+
#define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
118+
#define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */
119+
#define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
120+
#define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
121+
#define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
122+
#define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
123+
#define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */
124+
#define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
125+
#define SIIER_REOFE BIT(7) /* Frame Reception End Enable */
126+
#define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
127+
#define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
128+
#define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
129+
5130
enum {
6131
MSIOF_SPI_HOST,
7132
MSIOF_SPI_TARGET,

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