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1 | 1 | [ |
2 | 2 | { |
3 | 3 | "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
4 | | - "Counter": "0,1,2,3", |
5 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
6 | 4 | "EventCode": "0xC7", |
7 | 5 | "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", |
8 | 6 | "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
|
11 | 9 | }, |
12 | 10 | { |
13 | 11 | "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
14 | | - "Counter": "0,1,2,3", |
15 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
16 | 12 | "EventCode": "0xC7", |
17 | 13 | "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", |
18 | 14 | "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
|
21 | 17 | }, |
22 | 18 | { |
23 | 19 | "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
24 | | - "Counter": "0,1,2,3", |
25 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
26 | 20 | "EventCode": "0xC7", |
27 | 21 | "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", |
28 | 22 | "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
|
31 | 25 | }, |
32 | 26 | { |
33 | 27 | "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
34 | | - "Counter": "0,1,2,3", |
35 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
36 | 28 | "EventCode": "0xC7", |
37 | 29 | "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", |
38 | 30 | "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
|
41 | 33 | }, |
42 | 34 | { |
43 | 35 | "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
44 | | - "Counter": "0,1,2,3", |
45 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
46 | 36 | "EventCode": "0xC7", |
47 | 37 | "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", |
48 | 38 | "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
|
51 | 41 | }, |
52 | 42 | { |
53 | 43 | "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
54 | | - "Counter": "0,1,2,3", |
55 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
56 | 44 | "EventCode": "0xC7", |
57 | 45 | "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", |
58 | 46 | "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
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61 | 49 | }, |
62 | 50 | { |
63 | 51 | "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
64 | | - "Counter": "0,1,2,3", |
65 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
66 | 52 | "EventCode": "0xC7", |
67 | 53 | "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", |
68 | 54 | "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
|
71 | 57 | }, |
72 | 58 | { |
73 | 59 | "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
74 | | - "Counter": "0,1,2,3", |
75 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
76 | 60 | "EventCode": "0xC7", |
77 | 61 | "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", |
78 | 62 | "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
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81 | 65 | }, |
82 | 66 | { |
83 | 67 | "BriefDescription": "Cycles with any input/output SSE or FP assist", |
84 | | - "Counter": "0,1,2,3", |
85 | | - "CounterHTOff": "0,1,2,3,4,5,6,7", |
86 | 68 | "CounterMask": "1", |
87 | 69 | "EventCode": "0xCA", |
88 | 70 | "EventName": "FP_ASSIST.ANY", |
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