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Andre-ARMwens
Andre-ARM
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wens
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clk: sunxi-ng: a523: add interface mod clocks
Add the clocks driving what the user manual summarises under "interface" devices: raw NAND flash, MMC, SPI, EMAC, "IR" infrared, and the "GPADC" general purpose analogue/digital converter. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-10-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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‎drivers/clk/sunxi-ng/ccu-sun55i-a523.c‎

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,9 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M",
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pll_periph0_2x_hws, 8, 1, 0);
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static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M",
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pll_periph0_480M_hws, 3, 1, 0);
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static const struct clk_hw *pll_periph0_150M_hws[] = {
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&pll_periph0_150M_clk.hw
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};
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#define SUN55I_A523_PLL_PERIPH1_REG 0x028
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static struct ccu_nm pll_periph1_4x_clk = {
@@ -555,6 +558,132 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents,
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CLK_IS_CRITICAL,
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CCU_FEATURE_UPDATE_BIT);
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static const struct clk_parent_data nand_mmc_parents[] = {
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{ .fw_name = "hosc" },
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{ .hw = &pll_periph0_400M_clk.hw },
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{ .hw = &pll_periph0_300M_clk.hw },
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{ .hw = &pll_periph1_400M_clk.hw },
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{ .hw = &pll_periph1_300M_clk.hw },
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};
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static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk, "nand0", nand_mmc_parents,
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0x810,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand1_clk, "nand1", nand_mmc_parents,
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0x814,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents,
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0x830,
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0, 5, /* M */
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8, 5, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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2, /* post div */
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0);
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static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents,
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0x834,
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0, 5, /* M */
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8, 5, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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2, /* post div */
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0);
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static const struct clk_parent_data mmc2_parents[] = {
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{ .fw_name = "hosc" },
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{ .hw = &pll_periph0_800M_clk.common.hw },
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{ .hw = &pll_periph0_600M_clk.hw },
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{ .hw = &pll_periph1_800M_clk.common.hw },
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{ .hw = &pll_periph1_600M_clk.hw },
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};
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static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_parents,
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0x838,
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0, 5, /* M */
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8, 5, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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2, /* post div */
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0);
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static const struct clk_parent_data spi_parents[] = {
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{ .fw_name = "hosc" },
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{ .hw = &pll_periph0_300M_clk.hw },
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{ .hw = &pll_periph0_200M_clk.hw },
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{ .hw = &pll_periph1_300M_clk.hw },
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{ .hw = &pll_periph1_200M_clk.hw },
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};
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static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
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0, 5, /* M */
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8, 5, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
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0, 5, /* M */
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8, 5, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0x948,
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0, 5, /* M */
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8, 5, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_DUALDIV_MUX_GATE(spifc_clk, "spifc", nand_mmc_parents, 0x950,
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0, 5, /* M */
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8, 5, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac0_25M_clk, "emac0-25M",
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pll_periph0_150M_hws,
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0x970, BIT(31) | BIT(30), 6, 0);
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static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac1_25M_clk, "emac1-25M",
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pll_periph0_150M_hws,
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0x974, BIT(31) | BIT(30), 6, 0);
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static const struct clk_parent_data ir_rx_parents[] = {
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{ .fw_name = "losc" },
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{ .fw_name = "hosc" },
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};
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static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_rx_parents, 0x990,
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0, 5, /* M */
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24, 1, /* mux */
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BIT(31), /* gate */
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0);
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static const struct clk_parent_data ir_tx_ledc_parents[] = {
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{ .fw_name = "hosc" },
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{ .hw = &pll_periph1_600M_clk.hw },
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};
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static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents,
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0x9c0,
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0, 5, /* M */
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24, 1, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_M_WITH_GATE(gpadc0_clk, "gpadc0", "hosc", 0x9e0,
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0, 5, /* M */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_M_WITH_GATE(gpadc1_clk, "gpadc1", "hosc", 0x9e4,
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0, 5, /* M */
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BIT(31), /* gate */
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0);
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static const struct clk_parent_data losc_hosc_parents[] = {
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{ .fw_name = "hosc" },
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{ .fw_name = "losc" },
@@ -725,6 +854,21 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
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&hstimer5_clk.common,
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&iommu_clk.common,
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&dram_clk.common,
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&nand0_clk.common,
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&nand1_clk.common,
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&mmc0_clk.common,
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&mmc1_clk.common,
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&mmc2_clk.common,
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&spi0_clk.common,
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&spi1_clk.common,
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&spi2_clk.common,
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&spifc_clk.common,
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&emac0_25M_clk.common,
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&emac1_25M_clk.common,
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&ir_rx_clk.common,
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&ir_tx_clk.common,
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&gpadc0_clk.common,
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&gpadc1_clk.common,
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&pcie_aux_clk.common,
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&hdmi_24M_clk.common,
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&hdmi_cec_32k_clk.common,
@@ -801,6 +945,21 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
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[CLK_HSTIMER5] = &hstimer5_clk.common.hw,
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[CLK_IOMMU] = &iommu_clk.common.hw,
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[CLK_DRAM] = &dram_clk.common.hw,
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[CLK_NAND0] = &nand0_clk.common.hw,
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[CLK_NAND1] = &nand1_clk.common.hw,
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[CLK_MMC0] = &mmc0_clk.common.hw,
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[CLK_MMC1] = &mmc1_clk.common.hw,
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[CLK_MMC2] = &mmc2_clk.common.hw,
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[CLK_SPI0] = &spi0_clk.common.hw,
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[CLK_SPI1] = &spi1_clk.common.hw,
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[CLK_SPI2] = &spi2_clk.common.hw,
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[CLK_SPIFC] = &spifc_clk.common.hw,
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[CLK_EMAC0_25M] = &emac0_25M_clk.common.hw,
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[CLK_EMAC1_25M] = &emac1_25M_clk.common.hw,
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[CLK_IR_RX] = &ir_rx_clk.common.hw,
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[CLK_IR_TX] = &ir_tx_clk.common.hw,
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[CLK_GPADC0] = &gpadc0_clk.common.hw,
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[CLK_GPADC1] = &gpadc1_clk.common.hw,
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[CLK_PCIE_AUX] = &pcie_aux_clk.common.hw,
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[CLK_HDMI_24M] = &hdmi_24M_clk.common.hw,
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[CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw,

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