Skip to content

Commit ed36fcd

Browse files
esmilConchuOD
esmil
authored and
ConchuOD
committed
reset: starfive: Extract the common JH71X0 reset code
Extract the common JH71X0 reset code for reusing them to support JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
1 parent 1ec3d20 commit ed36fcd

3 files changed

Lines changed: 76 additions & 54 deletions

File tree

‎drivers/reset/starfive/reset-starfive-jh7100.c‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,55 @@
1010

1111
#include "reset-starfive-jh71x0.h"
1212

13+
#include <dt-bindings/reset/starfive-jh7100.h>
14+
15+
/* register offsets */
16+
#define JH7100_RESET_ASSERT0 0x00
17+
#define JH7100_RESET_ASSERT1 0x04
18+
#define JH7100_RESET_ASSERT2 0x08
19+
#define JH7100_RESET_ASSERT3 0x0c
20+
#define JH7100_RESET_STATUS0 0x10
21+
#define JH7100_RESET_STATUS1 0x14
22+
#define JH7100_RESET_STATUS2 0x18
23+
#define JH7100_RESET_STATUS3 0x1c
24+
25+
/*
26+
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
27+
* line 32m + n, and writing a 0 deasserts the same line.
28+
* Most reset lines have their status inverted so a 0 bit in the STATUS
29+
* register means the line is asserted and a 1 means it's deasserted. A few
30+
* lines don't though, so store the expected value of the status registers when
31+
* all lines are asserted.
32+
*/
33+
static const u64 jh7100_reset_asserted[2] = {
34+
/* STATUS0 */
35+
BIT_ULL_MASK(JH7100_RST_U74) |
36+
BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
37+
BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
38+
/* STATUS1 */
39+
BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
40+
BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
41+
/* STATUS2 */
42+
BIT_ULL_MASK(JH7100_RST_E24) |
43+
/* STATUS3 */
44+
0,
45+
};
46+
47+
static int __init jh7100_reset_probe(struct platform_device *pdev)
48+
{
49+
void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
50+
51+
if (IS_ERR(base))
52+
return PTR_ERR(base);
53+
54+
return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
55+
base + JH7100_RESET_ASSERT0,
56+
base + JH7100_RESET_STATUS0,
57+
jh7100_reset_asserted,
58+
JH7100_RSTN_END,
59+
THIS_MODULE);
60+
}
61+
1362
static const struct of_device_id jh7100_reset_dt_ids[] = {
1463
{ .compatible = "starfive,jh7100-reset" },
1564
{ /* sentinel */ }

‎drivers/reset/starfive/reset-starfive-jh71x0.c‎

Lines changed: 23 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -10,51 +10,18 @@
1010
#include <linux/io.h>
1111
#include <linux/io-64-nonatomic-lo-hi.h>
1212
#include <linux/iopoll.h>
13-
#include <linux/platform_device.h>
1413
#include <linux/reset-controller.h>
1514
#include <linux/spinlock.h>
1615

1716
#include "reset-starfive-jh71x0.h"
1817

19-
#include <dt-bindings/reset/starfive-jh7100.h>
20-
21-
/* register offsets */
22-
#define JH7100_RESET_ASSERT0 0x00
23-
#define JH7100_RESET_ASSERT1 0x04
24-
#define JH7100_RESET_ASSERT2 0x08
25-
#define JH7100_RESET_ASSERT3 0x0c
26-
#define JH7100_RESET_STATUS0 0x10
27-
#define JH7100_RESET_STATUS1 0x14
28-
#define JH7100_RESET_STATUS2 0x18
29-
#define JH7100_RESET_STATUS3 0x1c
30-
31-
/*
32-
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
33-
* line 32m + n, and writing a 0 deasserts the same line.
34-
* Most reset lines have their status inverted so a 0 bit in the STATUS
35-
* register means the line is asserted and a 1 means it's deasserted. A few
36-
* lines don't though, so store the expected value of the status registers when
37-
* all lines are asserted.
38-
*/
39-
static const u64 jh7100_reset_asserted[2] = {
40-
/* STATUS0 */
41-
BIT_ULL_MASK(JH7100_RST_U74) |
42-
BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
43-
BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
44-
/* STATUS1 */
45-
BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
46-
BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
47-
/* STATUS2 */
48-
BIT_ULL_MASK(JH7100_RST_E24) |
49-
/* STATUS3 */
50-
0,
51-
};
52-
5318
struct jh7100_reset {
5419
struct reset_controller_dev rcdev;
5520
/* protect registers against concurrent read-modify-write */
5621
spinlock_t lock;
57-
void __iomem *base;
22+
void __iomem *assert;
23+
void __iomem *status;
24+
const u64 *asserted;
5825
};
5926

6027
static inline struct jh7100_reset *
@@ -69,9 +36,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
6936
struct jh7100_reset *data = jh7100_reset_from(rcdev);
7037
unsigned long offset = BIT_ULL_WORD(id);
7138
u64 mask = BIT_ULL_MASK(id);
72-
void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
73-
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
74-
u64 done = jh7100_reset_asserted[offset] & mask;
39+
void __iomem *reg_assert = data->assert + offset * sizeof(u64);
40+
void __iomem *reg_status = data->status + offset * sizeof(u64);
41+
u64 done = data->asserted ? data->asserted[offset] & mask : 0;
7542
u64 value;
7643
unsigned long flags;
7744
int ret;
@@ -125,10 +92,10 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
12592
struct jh7100_reset *data = jh7100_reset_from(rcdev);
12693
unsigned long offset = BIT_ULL_WORD(id);
12794
u64 mask = BIT_ULL_MASK(id);
128-
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
95+
void __iomem *reg_status = data->status + offset * sizeof(u64);
12996
u64 value = readq(reg_status);
13097

131-
return !((value ^ jh7100_reset_asserted[offset]) & mask);
98+
return !((value ^ data->asserted[offset]) & mask);
13299
}
133100

134101
static const struct reset_control_ops jh7100_reset_ops = {
@@ -138,25 +105,28 @@ static const struct reset_control_ops jh7100_reset_ops = {
138105
.status = jh7100_reset_status,
139106
};
140107

141-
int jh7100_reset_probe(struct platform_device *pdev)
108+
int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
109+
void __iomem *assert, void __iomem *status,
110+
const u64 *asserted, unsigned int nr_resets,
111+
struct module *owner)
142112
{
143113
struct jh7100_reset *data;
144114

145-
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
115+
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
146116
if (!data)
147117
return -ENOMEM;
148118

149-
data->base = devm_platform_ioremap_resource(pdev, 0);
150-
if (IS_ERR(data->base))
151-
return PTR_ERR(data->base);
152-
153119
data->rcdev.ops = &jh7100_reset_ops;
154-
data->rcdev.owner = THIS_MODULE;
155-
data->rcdev.nr_resets = JH7100_RSTN_END;
156-
data->rcdev.dev = &pdev->dev;
157-
data->rcdev.of_node = pdev->dev.of_node;
120+
data->rcdev.owner = owner;
121+
data->rcdev.nr_resets = nr_resets;
122+
data->rcdev.dev = dev;
123+
data->rcdev.of_node = of_node;
124+
158125
spin_lock_init(&data->lock);
126+
data->assert = assert;
127+
data->status = status;
128+
data->asserted = asserted;
159129

160-
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
130+
return devm_reset_controller_register(dev, &data->rcdev);
161131
}
162-
EXPORT_SYMBOL_GPL(jh7100_reset_probe);
132+
EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);

‎drivers/reset/starfive/reset-starfive-jh71x0.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,9 @@
66
#ifndef __RESET_STARFIVE_JH71X0_H
77
#define __RESET_STARFIVE_JH71X0_H
88

9-
int jh7100_reset_probe(struct platform_device *pdev);
9+
int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
10+
void __iomem *assert, void __iomem *status,
11+
const u64 *asserted, unsigned int nr_resets,
12+
struct module *owner);
1013

1114
#endif /* __RESET_STARFIVE_JH71X0_H */

0 commit comments

Comments
 (0)