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arm64: dts: qcom: sc8280xp: Add GPU related nodes
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the SC8280XP. Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230614142204.2675653-2-quic_bjorande@quicinc.com
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‎arch/arm64/boot/dts/qcom/sa8540p.dtsi‎

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};
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};
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&gpucc {
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status = "disabled";
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};
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&gpu_smmu {
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status = "disabled";
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};
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&pcie2a {
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compatible = "qcom,pcie-sa8540p";
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‎arch/arm64/boot/dts/qcom/sc8280xp.dtsi‎

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#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
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#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
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#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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reg = <0x0 0x01fc0000 0x0 0x30000>;
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};
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gpu: gpu@3d00000 {
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compatible = "qcom,adreno-690.0", "qcom,adreno";
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reg = <0 0x03d00000 0 0x40000>,
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<0 0x03d9e000 0 0x1000>,
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<0 0x03d61000 0 0x800>;
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reg-names = "kgsl_3d0_reg_memory",
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"cx_mem",
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"cx_dbgc";
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interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
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operating-points-v2 = <&gpu_opp_table>;
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qcom,gmu = <&gmu>;
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interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "gfx-mem";
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#cooling-cells = <2>;
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status = "disabled";
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gpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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opp-peak-kBps = <451000>;
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};
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opp-410000000 {
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opp-hz = /bits/ 64 <410000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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opp-peak-kBps = <1555000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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opp-peak-kBps = <1555000>;
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};
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opp-547000000 {
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opp-hz = /bits/ 64 <547000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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opp-peak-kBps = <1555000>;
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};
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opp-606000000 {
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opp-hz = /bits/ 64 <606000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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opp-peak-kBps = <2736000>;
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};
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opp-640000000 {
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opp-hz = /bits/ 64 <640000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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opp-peak-kBps = <2736000>;
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};
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opp-655000000 {
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opp-hz = /bits/ 64 <655000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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opp-peak-kBps = <2736000>;
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};
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opp-690000000 {
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opp-hz = /bits/ 64 <690000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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opp-peak-kBps = <2736000>;
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};
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};
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};
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gmu: gmu@3d6a000 {
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compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
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reg = <0 0x03d6a000 0 0x34000>,
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<0 0x03de0000 0 0x10000>,
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<0 0x0b290000 0 0x10000>;
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reg-names = "gmu", "rscc", "gmu_pdc";
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
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clock-names = "gmu",
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"cxo",
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"axi",
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"memnoc",
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"ahb",
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"hub",
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"smmu_vote";
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power-domains = <&gpucc GPU_CC_CX_GDSC>,
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<&gpucc GPU_CC_GX_GDSC>;
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power-domain-names = "cx",
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"gx";
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iommus = <&gpu_smmu 5 0xc00>;
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operating-points-v2 = <&gmu_opp_table>;
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gmu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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};
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};
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gpucc: clock-controller@3d90000 {
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compatible = "qcom,sc8280xp-gpucc";
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reg = <0 0x03d90000 0 0x9000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
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clock-names = "bi_tcxo",
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"gcc_gpu_gpll0_clk_src",
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"gcc_gpu_gpll0_div_clk_src";
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power-domains = <&rpmhpd SC8280XP_GFX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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gpu_smmu: iommu@3da0000 {
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compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
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"qcom,smmu-500", "arm,mmu-500";
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reg = <0 0x03da0000 0 0x20000>;
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#iommu-cells = <2>;
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#global-interrupts = <2>;
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interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&gpucc GPU_CC_HUB_AON_CLK>;
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clock-names = "gcc_gpu_memnoc_gfx_clk",
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"gcc_gpu_snoc_dvm_gfx_clk",
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"gpu_cc_ahb_clk",
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"gpu_cc_hlos1_vote_gpu_smmu_clk",
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"gpu_cc_cx_gmu_clk",
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"gpu_cc_hub_cx_int_clk",
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"gpu_cc_hub_aon_clk";
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power-domains = <&gpucc GPU_CC_CX_GDSC>;
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dma-coherent;
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};
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usb_0_hsphy: phy@88e5000 {
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compatible = "qcom,sc8280xp-usb-hs-phy",
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"qcom,usb-snps-hs-5nm-phy";

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