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Dinh Nguyenbebarino
Dinh Nguyen
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bebarino
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clk: agilex/stratix10: remove noc_clk
Early documentation had a noc_clk, but in reality, it's just the noc_free_clk. Remove the noc_clk clock and just use the noc_free_clk. Fixes: 80c6b7a ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent 6efb943 commit efbe21d

2 files changed

Lines changed: 30 additions & 34 deletions

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‎drivers/clk/socfpga/clk-agilex.c‎

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -222,11 +222,9 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
222222
{ AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
223223
0, 0x3C, 0, 0, 0},
224224
{ AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
225-
0, 0x40, 0, 0, 1},
226-
{ AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
227-
0, 4, 0, 0},
228-
{ AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
229-
0, 0, 0, 0x30, 1},
225+
0, 0x40, 0, 0, 0},
226+
{ AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
227+
0, 4, 0x30, 1},
230228
{ AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
231229
0, 0xD4, 0, 0x88, 0},
232230
{ AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
@@ -252,24 +250,24 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
252250
0, 0, 0, 0, 0, 0, 4},
253251
{ AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
254252
0, 0, 0, 0, 0, 0, 2},
255-
{ AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,
256-
1, 0x44, 0, 2, 0, 0, 0},
257-
{ AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24,
258-
2, 0x44, 8, 2, 0, 0, 0},
253+
{ AGILEX_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
254+
1, 0x44, 0, 2, 0x30, 1, 0},
255+
{ AGILEX_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
256+
2, 0x44, 8, 2, 0x30, 1, 0},
259257
/*
260258
* The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them
261259
* being the SP timers, thus cannot get gated.
262260
*/
263-
{ AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24,
264-
3, 0x44, 16, 2, 0, 0, 0},
265-
{ AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24,
266-
4, 0x44, 24, 2, 0, 0, 0},
267-
{ AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24,
268-
4, 0x44, 26, 2, 0, 0, 0},
261+
{ AGILEX_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x24,
262+
3, 0x44, 16, 2, 0x30, 1, 0},
263+
{ AGILEX_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
264+
4, 0x44, 24, 2, 0x30, 1, 0},
265+
{ AGILEX_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
266+
4, 0x44, 26, 2, 0x30, 1, 0},
269267
{ AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
270268
4, 0x44, 28, 1, 0, 0, 0},
271-
{ AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24,
272-
5, 0, 0, 0, 0, 0, 0},
269+
{ AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
270+
5, 0, 0, 0, 0x30, 1, 0},
273271
{ AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24,
274272
6, 0, 0, 0, 0, 0, 0},
275273
{ AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,

‎drivers/clk/socfpga/clk-s10.c‎

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
167167
{ STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
168168
0, 0x48, 0, 0, 0},
169169
{ STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
170-
0, 0x4C, 0, 0, 0},
170+
0, 0x4C, 0, 0x3C, 1},
171171
{ STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
172172
0x50, 0, 0, 0},
173173
{ STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
@@ -200,10 +200,8 @@ static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
200200
0, 0xD4, 0, 0, 0},
201201
{ STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
202202
0xD8, 0, 0, 0},
203-
{ STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
204-
0, 4, 0, 0},
205-
{ STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
206-
0, 0, 0, 0x3C, 1},
203+
{ STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
204+
0, 4, 0x3C, 1},
207205
{ STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
208206
0, 0, 2, 0xB0, 0},
209207
{ STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
@@ -227,20 +225,20 @@ static const struct stratix10_gate_clock s10_gate_clks[] = {
227225
0, 0, 0, 0, 0, 0, 4},
228226
{ STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30,
229227
0, 0, 0, 0, 0, 0, 2},
230-
{ STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30,
231-
1, 0x70, 0, 2, 0, 0, 0},
232-
{ STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30,
233-
2, 0x70, 8, 2, 0, 0, 0},
234-
{ STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30,
235-
3, 0x70, 16, 2, 0, 0, 0},
236-
{ STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30,
237-
4, 0x70, 24, 2, 0, 0, 0},
238-
{ STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30,
239-
4, 0x70, 26, 2, 0, 0, 0},
228+
{ STRATIX10_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
229+
1, 0x70, 0, 2, 0x3C, 1, 0},
230+
{ STRATIX10_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
231+
2, 0x70, 8, 2, 0x3C, 1, 0},
232+
{ STRATIX10_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x30,
233+
3, 0x70, 16, 2, 0x3C, 1, 0},
234+
{ STRATIX10_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
235+
4, 0x70, 24, 2, 0x3C, 1, 0},
236+
{ STRATIX10_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
237+
4, 0x70, 26, 2, 0x3C, 1, 0},
240238
{ STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30,
241239
4, 0x70, 28, 1, 0, 0, 0},
242-
{ STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30,
243-
5, 0, 0, 0, 0, 0, 0},
240+
{ STRATIX10_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
241+
5, 0, 0, 0, 0x3C, 1, 0},
244242
{ STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30,
245243
6, 0, 0, 0, 0, 0, 0},
246244
{ STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,

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