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Johnson Wangbroonie
Johnson Wang
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broonie
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regulator: mt6366: Add support for MT6366 regulator
The MT6366 is a regulator found on boards based on MediaTek MT8186 and probably other SoCs. It is a so called pmic and connects as a slave to SoC using SPI, wrapped inside the pmic-wrapper. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220401080212.27383-2-johnson.wang@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
1 parent f704882 commit f0e3c62

2 files changed

Lines changed: 253 additions & 5 deletions

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‎drivers/regulator/mt6358-regulator.c‎

Lines changed: 208 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,102 @@ struct mt6358_regulator_info {
130130
.qi = BIT(15), \
131131
}
132132

133+
#define MT6366_BUCK(match, vreg, min, max, step, \
134+
volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \
135+
_modeset_reg, _modeset_shift) \
136+
[MT6366_ID_##vreg] = { \
137+
.desc = { \
138+
.name = #vreg, \
139+
.of_match = of_match_ptr(match), \
140+
.ops = &mt6358_volt_range_ops, \
141+
.type = REGULATOR_VOLTAGE, \
142+
.id = MT6366_ID_##vreg, \
143+
.owner = THIS_MODULE, \
144+
.n_voltages = ((max) - (min)) / (step) + 1, \
145+
.linear_ranges = volt_ranges, \
146+
.n_linear_ranges = ARRAY_SIZE(volt_ranges), \
147+
.vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
148+
.vsel_mask = vosel_mask, \
149+
.enable_reg = MT6358_BUCK_##vreg##_CON0, \
150+
.enable_mask = BIT(0), \
151+
.of_map_mode = mt6358_map_mode, \
152+
}, \
153+
.status_reg = MT6358_BUCK_##vreg##_DBG1, \
154+
.qi = BIT(0), \
155+
.da_vsel_reg = _da_vsel_reg, \
156+
.da_vsel_mask = _da_vsel_mask, \
157+
.modeset_reg = _modeset_reg, \
158+
.modeset_mask = BIT(_modeset_shift), \
159+
}
160+
161+
#define MT6366_LDO(match, vreg, ldo_volt_table, \
162+
ldo_index_table, enreg, enbit, vosel, \
163+
vosel_mask) \
164+
[MT6366_ID_##vreg] = { \
165+
.desc = { \
166+
.name = #vreg, \
167+
.of_match = of_match_ptr(match), \
168+
.ops = &mt6358_volt_table_ops, \
169+
.type = REGULATOR_VOLTAGE, \
170+
.id = MT6366_ID_##vreg, \
171+
.owner = THIS_MODULE, \
172+
.n_voltages = ARRAY_SIZE(ldo_volt_table), \
173+
.volt_table = ldo_volt_table, \
174+
.vsel_reg = vosel, \
175+
.vsel_mask = vosel_mask, \
176+
.enable_reg = enreg, \
177+
.enable_mask = BIT(enbit), \
178+
}, \
179+
.status_reg = MT6358_LDO_##vreg##_CON1, \
180+
.qi = BIT(15), \
181+
.index_table = ldo_index_table, \
182+
.n_table = ARRAY_SIZE(ldo_index_table), \
183+
}
184+
185+
#define MT6366_LDO1(match, vreg, min, max, step, \
186+
volt_ranges, _da_vsel_reg, _da_vsel_mask, \
187+
vosel, vosel_mask) \
188+
[MT6366_ID_##vreg] = { \
189+
.desc = { \
190+
.name = #vreg, \
191+
.of_match = of_match_ptr(match), \
192+
.ops = &mt6358_volt_range_ops, \
193+
.type = REGULATOR_VOLTAGE, \
194+
.id = MT6366_ID_##vreg, \
195+
.owner = THIS_MODULE, \
196+
.n_voltages = ((max) - (min)) / (step) + 1, \
197+
.linear_ranges = volt_ranges, \
198+
.n_linear_ranges = ARRAY_SIZE(volt_ranges), \
199+
.vsel_reg = vosel, \
200+
.vsel_mask = vosel_mask, \
201+
.enable_reg = MT6358_LDO_##vreg##_CON0, \
202+
.enable_mask = BIT(0), \
203+
}, \
204+
.da_vsel_reg = _da_vsel_reg, \
205+
.da_vsel_mask = _da_vsel_mask, \
206+
.status_reg = MT6358_LDO_##vreg##_DBG1, \
207+
.qi = BIT(0), \
208+
}
209+
210+
#define MT6366_REG_FIXED(match, vreg, \
211+
enreg, enbit, volt) \
212+
[MT6366_ID_##vreg] = { \
213+
.desc = { \
214+
.name = #vreg, \
215+
.of_match = of_match_ptr(match), \
216+
.ops = &mt6358_volt_fixed_ops, \
217+
.type = REGULATOR_VOLTAGE, \
218+
.id = MT6366_ID_##vreg, \
219+
.owner = THIS_MODULE, \
220+
.n_voltages = 1, \
221+
.enable_reg = enreg, \
222+
.enable_mask = BIT(enbit), \
223+
.min_uV = volt, \
224+
}, \
225+
.status_reg = MT6358_LDO_##vreg##_CON1, \
226+
.qi = BIT(15), \
227+
}
228+
133229
static const struct linear_range buck_volt_range1[] = {
134230
REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
135231
};
@@ -409,6 +505,9 @@ static struct mt6358_regulator_info mt6358_regulators[] = {
409505
MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
410506
buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
411507
MT6358_VCORE_VGPU_ANA_CON0, 1),
508+
MT6358_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250,
509+
buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f,
510+
MT6358_VCORE_VGPU_ANA_CON0, 1),
412511
MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
413512
buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
414513
MT6358_VPA_ANA_CON0, 3),
@@ -488,6 +587,10 @@ static struct mt6358_regulator_info mt6358_regulators[] = {
488587
MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
489588
buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
490589
MT6358_LDO_VSRAM_CON2, 0x7f),
590+
MT6358_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000,
591+
1293750, 6250, buck_volt_range1,
592+
MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f,
593+
MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f),
491594
MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
492595
buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
493596
MT6358_LDO_VSRAM_CON3, 0x7f),
@@ -496,24 +599,124 @@ static struct mt6358_regulator_info mt6358_regulators[] = {
496599
MT6358_LDO_VSRAM_CON1, 0x7f),
497600
};
498601

602+
/* The array is indexed by id(MT6366_ID_XXX) */
603+
static struct mt6358_regulator_info mt6366_regulators[] = {
604+
MT6366_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
605+
buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
606+
MT6358_VDRAM1_ANA_CON0, 8),
607+
MT6366_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
608+
buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
609+
MT6358_VCORE_VGPU_ANA_CON0, 1),
610+
MT6366_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250,
611+
buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f,
612+
MT6358_VCORE_VGPU_ANA_CON0, 1),
613+
MT6366_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
614+
buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
615+
MT6358_VPA_ANA_CON0, 3),
616+
MT6366_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
617+
buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
618+
MT6358_VPROC_ANA_CON0, 1),
619+
MT6366_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
620+
buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
621+
MT6358_VPROC_ANA_CON0, 2),
622+
MT6366_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
623+
buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f,
624+
MT6358_VCORE_VGPU_ANA_CON0, 2),
625+
MT6366_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
626+
buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f,
627+
MT6358_VS2_ANA_CON0, 8),
628+
MT6366_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
629+
buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
630+
MT6358_VMODEM_ANA_CON0, 8),
631+
MT6366_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
632+
buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f,
633+
MT6358_VS1_ANA_CON0, 8),
634+
MT6366_REG_FIXED("ldo_vrf12", VRF12,
635+
MT6358_LDO_VRF12_CON0, 0, 1200000),
636+
MT6366_REG_FIXED("ldo_vio18", VIO18,
637+
MT6358_LDO_VIO18_CON0, 0, 1800000),
638+
MT6366_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
639+
MT6366_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
640+
MT6366_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
641+
MT6366_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
642+
MT6366_REG_FIXED("ldo_vaux18", VAUX18,
643+
MT6358_LDO_VAUX18_CON0, 0, 1800000),
644+
MT6366_REG_FIXED("ldo_vbif28", VBIF28,
645+
MT6358_LDO_VBIF28_CON0, 0, 2800000),
646+
MT6366_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
647+
MT6366_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
648+
MT6366_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
649+
MT6366_REG_FIXED("ldo_vaud28", VAUD28,
650+
MT6358_LDO_VAUD28_CON0, 0, 2800000),
651+
MT6366_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
652+
MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
653+
MT6366_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx,
654+
MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
655+
MT6366_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
656+
MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
657+
MT6366_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
658+
MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
659+
MT6366_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
660+
MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
661+
MT6366_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx,
662+
MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
663+
MT6366_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx,
664+
MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
665+
MT6366_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
666+
vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
667+
0, MT6358_VCN33_ANA_CON0, 0x300),
668+
MT6366_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
669+
vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
670+
0, MT6358_VCN33_ANA_CON0, 0x300),
671+
MT6366_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
672+
MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
673+
MT6366_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx,
674+
MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
675+
MT6366_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
676+
buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00,
677+
MT6358_LDO_VSRAM_CON0, 0x7f),
678+
MT6366_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
679+
buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
680+
MT6358_LDO_VSRAM_CON2, 0x7f),
681+
MT6366_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000,
682+
1293750, 6250, buck_volt_range1,
683+
MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f,
684+
MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f),
685+
MT6366_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
686+
buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
687+
MT6358_LDO_VSRAM_CON3, 0x7f),
688+
MT6366_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
689+
buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00,
690+
MT6358_LDO_VSRAM_CON1, 0x7f),
691+
};
692+
499693
static int mt6358_regulator_probe(struct platform_device *pdev)
500694
{
501695
struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
502696
struct regulator_config config = {};
503697
struct regulator_dev *rdev;
504-
int i;
698+
struct mt6358_regulator_info *mt6358_info;
699+
int i, max_regulator;
700+
701+
if (mt6397->chip_id == MT6366_CHIP_ID) {
702+
max_regulator = MT6366_MAX_REGULATOR;
703+
mt6358_info = mt6366_regulators;
704+
} else {
705+
max_regulator = MT6358_MAX_REGULATOR;
706+
mt6358_info = mt6358_regulators;
707+
}
505708

506-
for (i = 0; i < MT6358_MAX_REGULATOR; i++) {
709+
for (i = 0; i < max_regulator; i++) {
507710
config.dev = &pdev->dev;
508-
config.driver_data = &mt6358_regulators[i];
711+
config.driver_data = &mt6358_info[i];
509712
config.regmap = mt6397->regmap;
510713

511714
rdev = devm_regulator_register(&pdev->dev,
512-
&mt6358_regulators[i].desc,
715+
&mt6358_info[i].desc,
513716
&config);
514717
if (IS_ERR(rdev)) {
515718
dev_err(&pdev->dev, "failed to register %s\n",
516-
mt6358_regulators[i].desc.name);
719+
mt6358_info[i].desc.name);
517720
return PTR_ERR(rdev);
518721
}
519722
}

‎include/linux/regulator/mt6358-regulator.h‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,9 +48,54 @@ enum {
4848
MT6358_ID_VLDO28,
4949
MT6358_ID_VAUD28,
5050
MT6358_ID_VSIM2,
51+
MT6358_ID_VCORE_SSHUB,
52+
MT6358_ID_VSRAM_OTHERS_SSHUB,
5153
MT6358_ID_RG_MAX,
5254
};
5355

56+
enum {
57+
MT6366_ID_VDRAM1 = 0,
58+
MT6366_ID_VCORE,
59+
MT6366_ID_VPA,
60+
MT6366_ID_VPROC11,
61+
MT6366_ID_VPROC12,
62+
MT6366_ID_VGPU,
63+
MT6366_ID_VS2,
64+
MT6366_ID_VMODEM,
65+
MT6366_ID_VS1,
66+
MT6366_ID_VDRAM2,
67+
MT6366_ID_VSIM1,
68+
MT6366_ID_VIBR,
69+
MT6366_ID_VRF12,
70+
MT6366_ID_VIO18,
71+
MT6366_ID_VUSB,
72+
MT6366_ID_VCN18,
73+
MT6366_ID_VFE28,
74+
MT6366_ID_VSRAM_PROC11,
75+
MT6366_ID_VCN28,
76+
MT6366_ID_VSRAM_OTHERS,
77+
MT6366_ID_VSRAM_GPU,
78+
MT6366_ID_VXO22,
79+
MT6366_ID_VEFUSE,
80+
MT6366_ID_VAUX18,
81+
MT6366_ID_VMCH,
82+
MT6366_ID_VBIF28,
83+
MT6366_ID_VSRAM_PROC12,
84+
MT6366_ID_VEMC,
85+
MT6366_ID_VIO28,
86+
MT6366_ID_VA12,
87+
MT6366_ID_VRF18,
88+
MT6366_ID_VCN33_BT,
89+
MT6366_ID_VCN33_WIFI,
90+
MT6366_ID_VMC,
91+
MT6366_ID_VAUD28,
92+
MT6366_ID_VSIM2,
93+
MT6366_ID_VCORE_SSHUB,
94+
MT6366_ID_VSRAM_OTHERS_SSHUB,
95+
MT6366_ID_RG_MAX,
96+
};
97+
5498
#define MT6358_MAX_REGULATOR MT6358_ID_RG_MAX
99+
#define MT6366_MAX_REGULATOR MT6366_ID_RG_MAX
55100

56101
#endif /* __LINUX_REGULATOR_MT6358_H */

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