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tinghan-shenmathieupoirier
tinghan-shen
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mathieupoirier
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remoteproc: mediatek: Fix side effect of mt8195 sram power on
The definition of L1TCM_SRAM_PDN bits on mt8195 is different to mt8192. L1TCM_SRAM_PDN bits[3:0] control the power of mt8195 L1TCM SRAM. L1TCM_SRAM_PDN bits[7:4] control the access path to EMI for SCP. These bits have to be powered on to allow EMI access for SCP. Bits[7:4] also affect audio DSP because audio DSP and SCP are placed on the same hardware bus. If SCP cannot access EMI, audio DSP is blocked too. L1TCM_SRAM_PDN bits[31:8] are not used. This fix removes modification of bits[7:4] when power on/off mt8195 SCP L1TCM. It's because the modification introduces a short period of time blocking audio DSP to access EMI. This was not a problem until we have to load both SCP module and audio DSP module. audio DSP needs to access EMI because it has source/data on DRAM. Audio DSP will have unexpected behavior when it accesses EMI and the SCP driver blocks the EMI path at the same time. Fixes: 79111df ("remoteproc: mediatek: Support mt8195 scp") Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220321060340.10975-1-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
1 parent ce522ba commit f20e232

2 files changed

Lines changed: 54 additions & 17 deletions

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‎drivers/remoteproc/mtk_common.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,8 @@
5454
#define MT8192_CORE0_WDT_IRQ 0x10030
5555
#define MT8192_CORE0_WDT_CFG 0x10034
5656

57+
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
58+
5759
#define SCP_FW_VER_LEN 32
5860
#define SCP_SHARE_BUFFER_SIZE 288
5961

‎drivers/remoteproc/mtk_scp.c‎

Lines changed: 52 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -365,22 +365,22 @@ static int mt8183_scp_before_load(struct mtk_scp *scp)
365365
return 0;
366366
}
367367

368-
static void mt8192_power_on_sram(void __iomem *addr)
368+
static void scp_sram_power_on(void __iomem *addr, u32 reserved_mask)
369369
{
370370
int i;
371371

372372
for (i = 31; i >= 0; i--)
373-
writel(GENMASK(i, 0), addr);
373+
writel(GENMASK(i, 0) & ~reserved_mask, addr);
374374
writel(0, addr);
375375
}
376376

377-
static void mt8192_power_off_sram(void __iomem *addr)
377+
static void scp_sram_power_off(void __iomem *addr, u32 reserved_mask)
378378
{
379379
int i;
380380

381381
writel(0, addr);
382382
for (i = 0; i < 32; i++)
383-
writel(GENMASK(i, 0), addr);
383+
writel(GENMASK(i, 0) & ~reserved_mask, addr);
384384
}
385385

386386
static int mt8186_scp_before_load(struct mtk_scp *scp)
@@ -393,7 +393,7 @@ static int mt8186_scp_before_load(struct mtk_scp *scp)
393393
writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
394394

395395
/* Turn on the power of SCP's SRAM before using it. Enable 1 block per time*/
396-
mt8192_power_on_sram(scp->reg_base + MT8183_SCP_SRAM_PDN);
396+
scp_sram_power_on(scp->reg_base + MT8183_SCP_SRAM_PDN, 0);
397397

398398
/* Initialize TCM before loading FW. */
399399
writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
@@ -412,11 +412,32 @@ static int mt8192_scp_before_load(struct mtk_scp *scp)
412412
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
413413

414414
/* enable SRAM clock */
415-
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_0);
416-
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_1);
417-
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_2);
418-
mt8192_power_on_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
419-
mt8192_power_on_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);
415+
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
416+
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
417+
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
418+
scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
419+
scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
420+
421+
/* enable MPU for all memory regions */
422+
writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
423+
424+
return 0;
425+
}
426+
427+
static int mt8195_scp_before_load(struct mtk_scp *scp)
428+
{
429+
/* clear SPM interrupt, SCP2SPM_IPC_CLR */
430+
writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
431+
432+
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
433+
434+
/* enable SRAM clock */
435+
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
436+
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
437+
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
438+
scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
439+
MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
440+
scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
420441

421442
/* enable MPU for all memory regions */
422443
writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
@@ -572,11 +593,25 @@ static void mt8183_scp_stop(struct mtk_scp *scp)
572593
static void mt8192_scp_stop(struct mtk_scp *scp)
573594
{
574595
/* Disable SRAM clock */
575-
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_0);
576-
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_1);
577-
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_2);
578-
mt8192_power_off_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
579-
mt8192_power_off_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);
596+
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
597+
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
598+
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
599+
scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
600+
scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
601+
602+
/* Disable SCP watchdog */
603+
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
604+
}
605+
606+
static void mt8195_scp_stop(struct mtk_scp *scp)
607+
{
608+
/* Disable SRAM clock */
609+
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
610+
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
611+
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
612+
scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
613+
MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
614+
scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
580615

581616
/* Disable SCP watchdog */
582617
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
@@ -922,11 +957,11 @@ static const struct mtk_scp_of_data mt8192_of_data = {
922957

923958
static const struct mtk_scp_of_data mt8195_of_data = {
924959
.scp_clk_get = mt8195_scp_clk_get,
925-
.scp_before_load = mt8192_scp_before_load,
960+
.scp_before_load = mt8195_scp_before_load,
926961
.scp_irq_handler = mt8192_scp_irq_handler,
927962
.scp_reset_assert = mt8192_scp_reset_assert,
928963
.scp_reset_deassert = mt8192_scp_reset_deassert,
929-
.scp_stop = mt8192_scp_stop,
964+
.scp_stop = mt8195_scp_stop,
930965
.scp_da_to_va = mt8192_scp_da_to_va,
931966
.host_to_scp_reg = MT8192_GIPC_IN_SET,
932967
.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,

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