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Merge branch 'for-next/perf' into for-next/core
* for-next/perf: (29 commits) perf/dwc_pcie: Fix use of uninitialized variable Documentation: hisi-pmu: Add introduction to HiSilicon V3 PMU Documentation: hisi-pmu: Fix of minor format error drivers/perf: hisi: Add support for L3C PMU v3 drivers/perf: hisi: Refactor the event configuration of L3C PMU drivers/perf: hisi: Extend the field of tt_core drivers/perf: hisi: Extract the event filter check of L3C PMU drivers/perf: hisi: Simplify the probe process of each L3C PMU version drivers/perf: hisi: Export hisi_uncore_pmu_isr() drivers/perf: hisi: Relax the event ID check in the framework perf: Fujitsu: Add the Uncore PMU driver perf/arm-cmn: Fix CMN S3 DTM offset perf: arm_spe: Prevent overflow in PERF_IDX2OFF() coresight: trbe: Prevent overflow in PERF_IDX2OFF() MAINTAINERS: Remove myself from HiSilicon PMU maintainers drivers/perf: hisi: Add support for HiSilicon MN PMU driver drivers/perf: hisi: Add support for HiSilicon NoC PMU perf: arm_pmuv3: Factor out PMCCNTR_EL0 use conditions arm64/boot: Enable EL2 requirements for SPE_FEAT_FDS arm64/boot: Factor out a macro to check SPE version ...
2 parents 77dfca7 + 2084660 commit f2d64a2

26 files changed

Lines changed: 2399 additions & 174 deletions

‎Documentation/admin-guide/perf/dwc_pcie_pmu.rst‎

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@@ -16,8 +16,8 @@ provides the following two features:
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- one 64-bit counter for Time Based Analysis (RX/TX data throughput and
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time spent in each low-power LTSSM state) and
19-
- one 32-bit counter for Event Counting (error and non-error events for
20-
a specified lane)
19+
- one 32-bit counter per event for Event Counting (error and non-error
20+
events for a specified lane)
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Note: There is no interrupt for counter overflow.
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‎Documentation/admin-guide/perf/fujitsu_uncore_pmu.rst‎

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.. SPDX-License-Identifier: GPL-2.0-only
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================================================
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Fujitsu Uncore Performance Monitoring Unit (PMU)
5+
================================================
6+
7+
This driver supports the Uncore MAC PMUs and the Uncore PCI PMUs found
8+
in Fujitsu chips.
9+
Each MAC PMU on these chips is exposed as a uncore perf PMU with device name
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mac_iod<iod>_mac<mac>_ch<ch>.
11+
And each PCI PMU on these chips is exposed as a uncore perf PMU with device name
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pci_iod<iod>_pci<pci>.
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14+
The driver provides a description of its available events and configuration
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options in sysfs, see /sys/bus/event_sources/devices/mac_iod<iod>_mac<mac>_ch<ch>/
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and /sys/bus/event_sources/devices/pci_iod<iod>_pci<pci>/.
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This driver exports:
18+
- formats, used by perf user space and other tools to configure events
19+
- events, used by perf user space and other tools to create events
20+
symbolically, e.g.:
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perf stat -a -e mac_iod0_mac0_ch0/event=0x21/ ls
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perf stat -a -e pci_iod0_pci0/event=0x24/ ls
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- cpumask, used by perf user space and other tools to know on which CPUs
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to open the events
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26+
This driver supports the following events for MAC:
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- cycles
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This event counts MAC cycles at MAC frequency.
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- read-count
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This event counts the number of read requests to MAC.
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- read-count-request
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This event counts the number of read requests including retry to MAC.
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- read-count-return
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This event counts the number of responses to read requests to MAC.
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- read-count-request-pftgt
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This event counts the number of read requests including retry with PFTGT
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flag.
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- read-count-request-normal
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This event counts the number of read requests including retry without PFTGT
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flag.
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- read-count-return-pftgt-hit
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This event counts the number of responses to read requests which hit the
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PFTGT buffer.
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- read-count-return-pftgt-miss
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This event counts the number of responses to read requests which miss the
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PFTGT buffer.
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- read-wait
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This event counts outstanding read requests issued by DDR memory controller
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per cycle.
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- write-count
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This event counts the number of write requests to MAC (including zero write,
52+
full write, partial write, write cancel).
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- write-count-write
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This event counts the number of full write requests to MAC (not including
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zero write).
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- write-count-pwrite
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This event counts the number of partial write requests to MAC.
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- memory-read-count
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This event counts the number of read requests from MAC to memory.
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- memory-write-count
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This event counts the number of full write requests from MAC to memory.
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- memory-pwrite-count
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This event counts the number of partial write requests from MAC to memory.
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- ea-mac
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This event counts energy consumption of MAC.
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- ea-memory
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This event counts energy consumption of memory.
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- ea-memory-mac-write
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This event counts the number of write requests from MAC to memory.
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- ea-ha
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This event counts energy consumption of HA.
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'ea' is the abbreviation for 'Energy Analyzer'.
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75+
Examples for use with perf::
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77+
perf stat -e mac_iod0_mac0_ch0/ea-mac/ ls
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79+
And, this driver supports the following events for PCI:
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- pci-port0-cycles
81+
This event counts PCI cycles at PCI frequency in port0.
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- pci-port0-read-count
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This event counts read transactions for data transfer in port0.
84+
- pci-port0-read-count-bus
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This event counts read transactions for bus usage in port0.
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- pci-port0-write-count
87+
This event counts write transactions for data transfer in port0.
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- pci-port0-write-count-bus
89+
This event counts write transactions for bus usage in port0.
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- pci-port1-cycles
91+
This event counts PCI cycles at PCI frequency in port1.
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- pci-port1-read-count
93+
This event counts read transactions for data transfer in port1.
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- pci-port1-read-count-bus
95+
This event counts read transactions for bus usage in port1.
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- pci-port1-write-count
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This event counts write transactions for data transfer in port1.
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- pci-port1-write-count-bus
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This event counts write transactions for bus usage in port1.
100+
- ea-pci
101+
This event counts energy consumption of PCI.
102+
103+
'ea' is the abbreviation for 'Energy Analyzer'.
104+
105+
Examples for use with perf::
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107+
perf stat -e pci_iod0_pci0/ea-pci/ ls
108+
109+
Given that these are uncore PMUs the driver does not support sampling, therefore
110+
"perf record" will not work. Per-task perf sessions are not supported.

‎Documentation/admin-guide/perf/hisi-pmu.rst‎

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@@ -18,9 +18,10 @@ HiSilicon SoC uncore PMU driver
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Each device PMU has separate registers for event counting, control and
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interrupt, and the PMU driver shall register perf PMU drivers like L3C,
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HHA and DDRC etc. The available events and configuration options shall
21-
be described in the sysfs, see:
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be described in the sysfs, see::
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>
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23-
/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
2425
The "perf list" command shall list the available events from sysfs.
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Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
@@ -112,6 +113,50 @@ uring channel. It is 2 bits. Some important codes are as follows:
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- 2'b00: default value, count the events which sent to the both uring and
113114
uring_ext channel;
114115

116+
6. ch: NoC PMU supports filtering the event counts of certain transaction
117+
channel with this option. The current supported channels are as follows:
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119+
- 3'b010: Request channel
120+
- 3'b100: Snoop channel
121+
- 3'b110: Response channel
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- 3'b111: Data channel
123+
124+
7. tt_en: NoC PMU supports counting only transactions that have tracetag set
125+
if this option is set. See the 2nd list for more information about tracetag.
126+
127+
For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are
128+
further divided into parts for finer granularity of tracing, each part has its
129+
own dedicated PMU, and all such PMUs together cover the monitoring job of events
130+
on particular uncore device. Such PMUs are described in sysfs with name format
131+
slightly changed::
132+
133+
/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}_{Z}/ddrc{Y}_{Z}/noc{Y}_{Z}>
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135+
Z is the sub-id, indicating different PMUs for part of hardware device.
136+
137+
Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU
138+
provides ``ext`` option to allow exploration of even finer granual statistics
139+
of L3C PMU. L3C PMU driver uses that as hint of termination when delivering
140+
perf command to hardware:
141+
142+
- ext=0: Default, could be used with event names.
143+
- ext=1 and ext=2: Must be used with event codes, event names are not supported.
144+
145+
An example of perf command could be::
146+
147+
$# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5
148+
149+
or::
150+
151+
$# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5
152+
153+
As above, ``hisi_sccl0_l3c1_0`` locates PMU of Super CPU CLuster 0, L3 cache 1
154+
pipe0.
155+
156+
First command locates the first part of L3C since ``ext=0`` is implied by
157+
default. Second command issues the counting on another part of L3C with the
158+
event ``0x1``.
159+
115160
Users could configure IDs to count data come from specific CCL/ICL, by setting
116161
srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
117162
tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not

‎Documentation/admin-guide/perf/index.rst‎

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@@ -29,3 +29,4 @@ Performance monitor support
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cxl
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ampere_cspmu
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mrvl-pem-pmu
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fujitsu_uncore_pmu

‎Documentation/arch/arm64/booting.rst‎

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@@ -466,6 +466,17 @@ Before jumping into the kernel, the following conditions must be met:
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- HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
467467
- HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
468468

469+
For CPUs with SPE data source filtering (FEAT_SPE_FDS):
470+
471+
- If EL3 is present:
472+
473+
- MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1.
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475+
- If the kernel is entered at EL1 and EL2 is present:
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477+
- HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
478+
- HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
479+
469480
For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):
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471482
- If the kernel is entered at EL1 and EL2 is present:

‎Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml‎

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@@ -33,6 +33,7 @@ properties:
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- items:
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- enum:
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- fsl,imx91-ddr-pmu
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- fsl,imx94-ddr-pmu
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- fsl,imx95-ddr-pmu
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- const: fsl,imx93-ddr-pmu
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‎MAINTAINERS‎

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@@ -9744,11 +9744,14 @@ F: drivers/video/fbdev/imxfb.c
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97459745
FREESCALE IMX DDR PMU DRIVER
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M: Frank Li <Frank.li@nxp.com>
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M: Xu Yang <xu.yang_2@nxp.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/admin-guide/perf/imx-ddr.rst
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F: Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
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F: drivers/perf/fsl_imx8_ddr_perf.c
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F: drivers/perf/fsl_imx9_ddr_perf.c
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F: tools/perf/pmu-events/arch/arm64/freescale/
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FREESCALE IMX I2C DRIVER
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M: Oleksij Rempel <o.rempel@pengutronix.de>
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F: drivers/net/ethernet/hisilicon/
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HISILICON PMU DRIVER
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M: Yicong Yang <yangyicong@hisilicon.com>
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M: Jonathan Cameron <jonathan.cameron@huawei.com>
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S: Supported
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W: http://www.hisilicon.com

‎arch/arm64/include/asm/el2_setup.h‎

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@@ -91,6 +91,14 @@
9191
msr cntvoff_el2, xzr // Clear virtual offset
9292
.endm
9393

94+
/* Branch to skip_label if SPE version is less than given version */
95+
.macro __spe_vers_imp skip_label, version, tmp
96+
mrs \tmp, id_aa64dfr0_el1
97+
ubfx \tmp, \tmp, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
98+
cmp \tmp, \version
99+
b.lt \skip_label
100+
.endm
101+
94102
.macro __init_el2_debug
95103
mrs x1, id_aa64dfr0_el1
96104
ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
@@ -103,8 +111,7 @@
103111
csel x2, xzr, x0, eq // all PMU counters from EL1
104112

105113
/* Statistical profiling */
106-
ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
107-
cbz x0, .Lskip_spe_\@ // Skip if SPE not present
114+
__spe_vers_imp .Lskip_spe_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x0 // Skip if SPE not present
108115

109116
mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
110117
and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT)
@@ -263,10 +270,8 @@
263270

264271
mov x0, xzr
265272
mov x2, xzr
266-
mrs x1, id_aa64dfr0_el1
267-
ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
268-
cmp x1, #3
269-
b.lt .Lskip_spe_fgt_\@
273+
/* If SPEv1p2 is implemented, */
274+
__spe_vers_imp .Lskip_spe_fgt_\@, #ID_AA64DFR0_EL1_PMSVer_V1P2, x1
270275
/* Disable PMSNEVFR_EL1 read and write traps */
271276
orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK
272277
orr x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK
@@ -387,6 +392,17 @@
387392
orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0
388393
orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1
389394
.Lskip_pmuv3p9_\@:
395+
/* If SPE is implemented, */
396+
__spe_vers_imp .Lskip_spefds_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x1
397+
/* we can read PMSIDR and */
398+
mrs_s x1, SYS_PMSIDR_EL1
399+
and x1, x1, #PMSIDR_EL1_FDS
400+
/* if FEAT_SPE_FDS is implemented, */
401+
cbz x1, .Lskip_spefds_\@
402+
/* disable traps of PMSDSFR to EL2. */
403+
orr x0, x0, #HDFGRTR2_EL2_nPMSDSFR_EL1
404+
405+
.Lskip_spefds_\@:
390406
msr_s SYS_HDFGRTR2_EL2, x0
391407
msr_s SYS_HDFGWTR2_EL2, x0
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msr_s SYS_HFGRTR2_EL2, xzr

‎arch/arm64/include/asm/sysreg.h‎

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@@ -344,15 +344,6 @@
344344
#define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56)
345345
#define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
346346

347-
/*** Statistical Profiling Extension ***/
348-
#define PMSEVFR_EL1_RES0_IMP \
349-
(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
350-
BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
351-
#define PMSEVFR_EL1_RES0_V1P1 \
352-
(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
353-
#define PMSEVFR_EL1_RES0_V1P2 \
354-
(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
355-
356347
/* Buffer error reporting */
357348
#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
358349
#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK

‎arch/arm64/tools/sysreg‎

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@@ -2994,11 +2994,20 @@ Field 0 RND
29942994
EndSysreg
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29962996
Sysreg PMSFCR_EL1 3 0 9 9 4
2997-
Res0 63:19
2997+
Res0 63:53
2998+
Field 52 SIMDm
2999+
Field 51 FPm
3000+
Field 50 STm
3001+
Field 49 LDm
3002+
Field 48 Bm
3003+
Res0 47:21
3004+
Field 20 SIMD
3005+
Field 19 FP
29983006
Field 18 ST
29993007
Field 17 LD
30003008
Field 16 B
3001-
Res0 15:4
3009+
Res0 15:5
3010+
Field 4 FDS
30023011
Field 3 FnE
30033012
Field 2 FL
30043013
Field 1 FT

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