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cometzeroSylwester Nawrocki
cometzero
authored and
Sylwester Nawrocki
committed
clk: samsung: exynosautov9: add cmu_peric0 clock support
CMU_PERIC0 provides clocks for USI0 ~ USI5 and USIx_I2C. USI0/1/2/3/4/5 have its own divider but USI_I2Cs share "dout_peric0_usi_i2c" divider. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220504075154.58819-9-chanho61.park@samsung.com
1 parent 65165b1 commit f2dd366

1 file changed

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‎drivers/clk/samsung/clk-exynosautov9.c‎

Lines changed: 254 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1134,6 +1134,257 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
11341134
.clk_name = "dout_clkcmu_fsys2_bus",
11351135
};
11361136

1137+
/* ---- CMU_PERIC0 --------------------------------------------------------- */
1138+
1139+
/* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1140+
#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1141+
#define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610
1142+
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000
1143+
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004
1144+
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008
1145+
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c
1146+
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010
1147+
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014
1148+
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018
1149+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800
1150+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804
1151+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808
1152+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c
1153+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810
1154+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814
1155+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818
1156+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014
1157+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018
1158+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024
1159+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028
1160+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c
1161+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030
1162+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034
1163+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038
1164+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c
1165+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040
1166+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c
1167+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020
1168+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044
1169+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048
1170+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
1171+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
1172+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
1173+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
1174+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
1175+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
1176+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
1177+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
1178+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
1179+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050
1180+
1181+
static const unsigned long peric0_clk_regs[] __initconst = {
1182+
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1183+
PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1184+
CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1185+
CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1186+
CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1187+
CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1188+
CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1189+
CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1190+
CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1191+
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1192+
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1193+
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1194+
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1195+
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1196+
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1197+
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1198+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1199+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1200+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1201+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1202+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1203+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1204+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1205+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1206+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1207+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1208+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1209+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1210+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1211+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
1212+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1213+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1214+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1215+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1216+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1217+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1218+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1219+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1220+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1221+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1222+
};
1223+
1224+
/* List of parent clocks for Muxes in CMU_PERIC0 */
1225+
PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" };
1226+
PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1227+
PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1228+
1229+
static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1230+
MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
1231+
mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
1232+
MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1233+
mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1234+
/* USI00 ~ USI05 */
1235+
MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1236+
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1237+
MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1238+
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1239+
MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1240+
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1241+
MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1242+
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1243+
MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1244+
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1245+
MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1246+
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1247+
/* USI_I2C */
1248+
MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1249+
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1250+
};
1251+
1252+
static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1253+
/* USI00 ~ USI05 */
1254+
DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1255+
"mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1256+
0, 4),
1257+
DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1258+
"mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1259+
0, 4),
1260+
DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1261+
"mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1262+
0, 4),
1263+
DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1264+
"mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1265+
0, 4),
1266+
DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1267+
"mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1268+
0, 4),
1269+
DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1270+
"mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1271+
0, 4),
1272+
/* USI_I2C */
1273+
DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1274+
"mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1275+
};
1276+
1277+
static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
1278+
/* IPCLK */
1279+
GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0",
1280+
"dout_peric0_usi00_usi",
1281+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1282+
21, 0, 0),
1283+
GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1",
1284+
"dout_peric0_usi_i2c",
1285+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1286+
21, 0, 0),
1287+
GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2",
1288+
"dout_peric0_usi01_usi",
1289+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1290+
21, 0, 0),
1291+
GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3",
1292+
"dout_peric0_usi_i2c",
1293+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1294+
21, 0, 0),
1295+
GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4",
1296+
"dout_peric0_usi02_usi",
1297+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1298+
21, 0, 0),
1299+
GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5",
1300+
"dout_peric0_usi_i2c",
1301+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1302+
21, 0, 0),
1303+
GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6",
1304+
"dout_peric0_usi03_usi",
1305+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1306+
21, 0, 0),
1307+
GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7",
1308+
"dout_peric0_usi_i2c",
1309+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1310+
21, 0, 0),
1311+
GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8",
1312+
"dout_peric0_usi04_usi",
1313+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1314+
21, 0, 0),
1315+
GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9",
1316+
"dout_peric0_usi_i2c",
1317+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1318+
21, 0, 0),
1319+
GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10",
1320+
"dout_peric0_usi05_usi",
1321+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1322+
21, 0, 0),
1323+
GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11",
1324+
"dout_peric0_usi_i2c",
1325+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1326+
21, 0, 0),
1327+
1328+
/* PCLK */
1329+
GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0",
1330+
"mout_peric0_bus_user",
1331+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1332+
21, 0, 0),
1333+
GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
1334+
"mout_peric0_bus_user",
1335+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1336+
21, 0, 0),
1337+
GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3",
1338+
"mout_peric0_bus_user",
1339+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1340+
21, 0, 0),
1341+
GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4",
1342+
"mout_peric0_bus_user",
1343+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1344+
21, 0, 0),
1345+
GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5",
1346+
"mout_peric0_bus_user",
1347+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1348+
21, 0, 0),
1349+
GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6",
1350+
"mout_peric0_bus_user",
1351+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1352+
21, 0, 0),
1353+
GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7",
1354+
"mout_peric0_bus_user",
1355+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1356+
21, 0, 0),
1357+
GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8",
1358+
"mout_peric0_bus_user",
1359+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1360+
21, 0, 0),
1361+
GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9",
1362+
"mout_peric0_bus_user",
1363+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1364+
21, 0, 0),
1365+
GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10",
1366+
"mout_peric0_bus_user",
1367+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1368+
21, 0, 0),
1369+
GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11",
1370+
"mout_peric0_bus_user",
1371+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1372+
21, 0, 0),
1373+
};
1374+
1375+
static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1376+
.mux_clks = peric0_mux_clks,
1377+
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1378+
.div_clks = peric0_div_clks,
1379+
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1380+
.gate_clks = peric0_gate_clks,
1381+
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
1382+
.nr_clk_ids = PERIC0_NR_CLK,
1383+
.clk_regs = peric0_clk_regs,
1384+
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
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.clk_name = "dout_clkcmu_peric0_bus",
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};
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/* ---- CMU_PERIS ---------------------------------------------------------- */
11381389

11391390
/* Register Offset definitions for CMU_PERIS (0x10020000) */
@@ -1202,6 +1453,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
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}, {
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.compatible = "samsung,exynosautov9-cmu-fsys2",
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.data = &fsys2_cmu_info,
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}, {
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.compatible = "samsung,exynosautov9-cmu-peric0",
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.data = &peric0_cmu_info,
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}, {
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.compatible = "samsung,exynosautov9-cmu-peris",
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.data = &peris_cmu_info,

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