1818#define SDHCI_VENDOR 0x78
1919#define SDHCI_VENDOR_ENHANCED_STRB 0x1
2020
21- #define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0)
22- #define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1)
21+ #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0)
22+ #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1)
23+
24+ #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0)
2325
2426#define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
2527
2628struct sdhci_brcmstb_priv {
2729 void __iomem * cfg_regs ;
28- bool has_cqe ;
30+ unsigned int flags ;
2931};
3032
3133struct brcmstb_match_priv {
3234 void (* hs400es )(struct mmc_host * mmc , struct mmc_ios * ios );
3335 struct sdhci_ops * ops ;
34- unsigned int flags ;
36+ const unsigned int flags ;
3537};
3638
3739static void sdhci_brcmstb_hs400es (struct mmc_host * mmc , struct mmc_ios * ios )
@@ -134,13 +136,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
134136};
135137
136138static struct brcmstb_match_priv match_priv_7425 = {
137- .flags = BRCMSTB_PRIV_FLAGS_NO_64BIT |
138- BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT ,
139+ .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT |
140+ BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT ,
139141 .ops = & sdhci_brcmstb_ops ,
140142};
141143
142144static struct brcmstb_match_priv match_priv_7445 = {
143- .flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT ,
145+ .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT ,
144146 .ops = & sdhci_brcmstb_ops ,
145147};
146148
@@ -176,7 +178,7 @@ static int sdhci_brcmstb_add_host(struct sdhci_host *host,
176178 bool dma64 ;
177179 int ret ;
178180
179- if (! priv -> has_cqe )
181+ if (( priv -> flags & BRCMSTB_PRIV_FLAGS_HAS_CQE ) == 0 )
180182 return sdhci_add_host (host );
181183
182184 dev_dbg (mmc_dev (host -> mmc ), "CQE is enabled\n" );
@@ -225,7 +227,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
225227 struct sdhci_brcmstb_priv * priv ;
226228 struct sdhci_host * host ;
227229 struct resource * iomem ;
228- bool has_cqe = false;
229230 struct clk * clk ;
230231 int res ;
231232
@@ -244,10 +245,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
244245 return res ;
245246
246247 memset (& brcmstb_pdata , 0 , sizeof (brcmstb_pdata ));
247- if (device_property_read_bool (& pdev -> dev , "supports-cqe" )) {
248- has_cqe = true;
249- match_priv -> ops -> irq = sdhci_brcmstb_cqhci_irq ;
250- }
251248 brcmstb_pdata .ops = match_priv -> ops ;
252249 host = sdhci_pltfm_init (pdev , & brcmstb_pdata ,
253250 sizeof (struct sdhci_brcmstb_priv ));
@@ -258,7 +255,10 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
258255
259256 pltfm_host = sdhci_priv (host );
260257 priv = sdhci_pltfm_priv (pltfm_host );
261- priv -> has_cqe = has_cqe ;
258+ if (device_property_read_bool (& pdev -> dev , "supports-cqe" )) {
259+ priv -> flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE ;
260+ match_priv -> ops -> irq = sdhci_brcmstb_cqhci_irq ;
261+ }
262262
263263 /* Map in the non-standard CFG registers */
264264 iomem = platform_get_resource (pdev , IORESOURCE_MEM , 1 );
@@ -287,14 +287,14 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
287287 * properties through mmc_of_parse().
288288 */
289289 host -> caps = sdhci_readl (host , SDHCI_CAPABILITIES );
290- if (match_priv -> flags & BRCMSTB_PRIV_FLAGS_NO_64BIT )
290+ if (match_priv -> flags & BRCMSTB_MATCH_FLAGS_NO_64BIT )
291291 host -> caps &= ~SDHCI_CAN_64BIT ;
292292 host -> caps1 = sdhci_readl (host , SDHCI_CAPABILITIES_1 );
293293 host -> caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
294294 SDHCI_SUPPORT_DDR50 );
295295 host -> quirks |= SDHCI_QUIRK_MISSING_CAPS ;
296296
297- if (match_priv -> flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT )
297+ if (match_priv -> flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT )
298298 host -> quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL ;
299299
300300 res = sdhci_brcmstb_add_host (host , priv );
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