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bebarinobebarino
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Merge tag 'renesas-clk-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add GPU clocks on R-Car V3U - Add USB3.0 clocks and resets on RZ/V2H and RZ/V2N - Add more serial (RSCI) clocks and resets on RZ/G3E - Add SPI clocks on RZ/T2H and RZ/N2H * tag 'renesas-clk-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g077: Add SPI module clocks clk: renesas: r9a09g056: Add USB3.0 clocks/resets clk: renesas: r9a09g057: Add USB3.0 clocks/resets clk: renesas: r9a09g047: Add RSCI clocks/resets dt-bindings: clock: renesas,r9a09g056-cpg: Add USB3.0 core clocks dt-bindings: clock: renesas,r9a09g057-cpg: Add USB3.0 core clocks clk: renesas: r9a06g032: Fix memory leak in error path clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration clk: renesas: r9a09g077: Remove stray blank line clk: renesas: r9a09g077: Propagate rate changes to parent clocks clk: renesas: r8a779a0: Add 3DGE module clock clk: renesas: r8a779a0: Add ZG Core clock clk: renesas: rcar-gen4: Add support for clock dividers in FRQCRB dt-bindings: clock: r8a779a0: Add ZG core clock
2 parents 1f2d68c + 5fb2f67 commit f700b88

10 files changed

Lines changed: 209 additions & 24 deletions

File tree

‎drivers/clk/renesas/r8a779a0-cpg-mssr.c‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626

2727
enum clk_ids {
2828
/* Core Clock Outputs exported to DT */
29-
LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
29+
LAST_DT_CORE_CLK = R8A779A0_CLK_ZG,
3030

3131
/* External Input Clocks */
3232
CLK_EXTAL,
@@ -39,6 +39,7 @@ enum clk_ids {
3939
CLK_PLL21,
4040
CLK_PLL30,
4141
CLK_PLL31,
42+
CLK_PLL4,
4243
CLK_PLL5,
4344
CLK_PLL1_DIV2,
4445
CLK_PLL20_DIV2,
@@ -65,6 +66,7 @@ enum clk_ids {
6566
#define CPG_PLL21CR 0x0838 /* PLL21 Control Register */
6667
#define CPG_PLL30CR 0x083c /* PLL30 Control Register */
6768
#define CPG_PLL31CR 0x0840 /* PLL31 Control Register */
69+
#define CPG_PLL4CR 0x0844 /* PLL4 Control Register */
6870

6971
static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
7072
/* External Clock Inputs */
@@ -79,6 +81,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
7981
DEF_PLL(".pll21", CLK_PLL21, CPG_PLL21CR),
8082
DEF_PLL(".pll30", CLK_PLL30, CPG_PLL30CR),
8183
DEF_PLL(".pll31", CLK_PLL31, CPG_PLL31CR),
84+
DEF_PLL(".pll4", CLK_PLL4, CPG_PLL4CR),
8285

8386
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
8487
DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
@@ -98,6 +101,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
98101
/* Core Clock Outputs */
99102
DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
100103
DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8),
104+
DEF_GEN4_Z("zg", R8A779A0_CLK_ZG, CLK_TYPE_GEN4_Z, CLK_PLL4, 2, 88),
101105
DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
102106
DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
103107
DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
@@ -138,6 +142,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
138142
};
139143

140144
static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
145+
DEF_MOD("3dge", 0, R8A779A0_CLK_ZG),
141146
DEF_MOD("isp0", 16, R8A779A0_CLK_S1D1),
142147
DEF_MOD("isp1", 17, R8A779A0_CLK_S1D1),
143148
DEF_MOD("isp2", 18, R8A779A0_CLK_S1D1),

‎drivers/clk/renesas/r9a06g032-clocks.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1333,9 +1333,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
13331333
if (IS_ERR(mclk))
13341334
return PTR_ERR(mclk);
13351335

1336-
clocks->reg = of_iomap(np, 0);
1337-
if (WARN_ON(!clocks->reg))
1338-
return -ENOMEM;
1336+
clocks->reg = devm_of_iomap(dev, np, 0, NULL);
1337+
if (IS_ERR(clocks->reg))
1338+
return PTR_ERR(clocks->reg);
13391339

13401340
r9a06g032_init_h2mode(clocks);
13411341

‎drivers/clk/renesas/r9a09g047-cpg.c‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,9 @@ enum clk_ids {
4444
CLK_PLLCLN_DIV8,
4545
CLK_PLLCLN_DIV16,
4646
CLK_PLLCLN_DIV20,
47+
CLK_PLLCLN_DIV64,
48+
CLK_PLLCLN_DIV256,
49+
CLK_PLLCLN_DIV1024,
4750
CLK_PLLDTY_ACPU,
4851
CLK_PLLDTY_ACPU_DIV2,
4952
CLK_PLLDTY_ACPU_DIV4,
@@ -142,6 +145,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
142145
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
143146
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
144147
DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
148+
DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
149+
DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
150+
DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
145151

146152
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
147153
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
@@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
218224
BUS_MSTOP(5, BIT(13))),
219225
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
220226
BUS_MSTOP(5, BIT(13))),
227+
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
228+
BUS_MSTOP(11, BIT(3))),
229+
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
230+
BUS_MSTOP(11, BIT(3))),
231+
DEF_MOD("rsci0_ps_ps3_n", CLK_PLLCLN_DIV1024, 5, 15, 2, 31,
232+
BUS_MSTOP(11, BIT(3))),
233+
DEF_MOD("rsci0_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 0, 3, 0,
234+
BUS_MSTOP(11, BIT(3))),
235+
DEF_MOD("rsci0_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 1, 3, 1,
236+
BUS_MSTOP(11, BIT(3))),
237+
DEF_MOD("rsci1_pclk", CLK_PLLCLN_DIV16, 6, 2, 3, 2,
238+
BUS_MSTOP(11, BIT(4))),
239+
DEF_MOD("rsci1_tclk", CLK_PLLCLN_DIV16, 6, 3, 3, 3,
240+
BUS_MSTOP(11, BIT(4))),
241+
DEF_MOD("rsci1_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
242+
BUS_MSTOP(11, BIT(4))),
243+
DEF_MOD("rsci1_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 5, 3, 5,
244+
BUS_MSTOP(11, BIT(4))),
245+
DEF_MOD("rsci1_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 6, 3, 6,
246+
BUS_MSTOP(11, BIT(4))),
247+
DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
248+
BUS_MSTOP(11, BIT(5))),
249+
DEF_MOD("rsci2_tclk", CLK_PLLCLN_DIV16, 6, 8, 3, 8,
250+
BUS_MSTOP(11, BIT(5))),
251+
DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
252+
BUS_MSTOP(11, BIT(5))),
253+
DEF_MOD("rsci2_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 10, 3, 10,
254+
BUS_MSTOP(11, BIT(5))),
255+
DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11,
256+
BUS_MSTOP(11, BIT(5))),
257+
DEF_MOD("rsci3_pclk", CLK_PLLCLN_DIV16, 6, 12, 3, 12,
258+
BUS_MSTOP(11, BIT(6))),
259+
DEF_MOD("rsci3_tclk", CLK_PLLCLN_DIV16, 6, 13, 3, 13,
260+
BUS_MSTOP(11, BIT(6))),
261+
DEF_MOD("rsci3_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
262+
BUS_MSTOP(11, BIT(6))),
263+
DEF_MOD("rsci3_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 15, 3, 15,
264+
BUS_MSTOP(11, BIT(6))),
265+
DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
266+
BUS_MSTOP(11, BIT(6))),
267+
DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
268+
BUS_MSTOP(11, BIT(7))),
269+
DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18,
270+
BUS_MSTOP(11, BIT(7))),
271+
DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
272+
BUS_MSTOP(11, BIT(7))),
273+
DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20,
274+
BUS_MSTOP(11, BIT(7))),
275+
DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
276+
BUS_MSTOP(11, BIT(7))),
277+
DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
278+
BUS_MSTOP(11, BIT(8))),
279+
DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23,
280+
BUS_MSTOP(11, BIT(8))),
281+
DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
282+
BUS_MSTOP(11, BIT(8))),
283+
DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25,
284+
BUS_MSTOP(11, BIT(8))),
285+
DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26,
286+
BUS_MSTOP(11, BIT(8))),
287+
DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27,
288+
BUS_MSTOP(11, BIT(9))),
289+
DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28,
290+
BUS_MSTOP(11, BIT(9))),
291+
DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
292+
BUS_MSTOP(11, BIT(9))),
293+
DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30,
294+
BUS_MSTOP(11, BIT(9))),
295+
DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31,
296+
BUS_MSTOP(11, BIT(9))),
297+
DEF_MOD("rsci7_pclk", CLK_PLLCLN_DIV16, 8, 0, 4, 0,
298+
BUS_MSTOP(11, BIT(10))),
299+
DEF_MOD("rsci7_tclk", CLK_PLLCLN_DIV16, 8, 1, 4, 1,
300+
BUS_MSTOP(11, BIT(10))),
301+
DEF_MOD("rsci7_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 2, 4, 2,
302+
BUS_MSTOP(11, BIT(10))),
303+
DEF_MOD("rsci7_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 3, 4, 3,
304+
BUS_MSTOP(11, BIT(10))),
305+
DEF_MOD("rsci7_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 4, 4, 4,
306+
BUS_MSTOP(11, BIT(10))),
307+
DEF_MOD("rsci8_pclk", CLK_PLLCLN_DIV16, 8, 5, 4, 5,
308+
BUS_MSTOP(11, BIT(11))),
309+
DEF_MOD("rsci8_tclk", CLK_PLLCLN_DIV16, 8, 6, 4, 6,
310+
BUS_MSTOP(11, BIT(11))),
311+
DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
312+
BUS_MSTOP(11, BIT(11))),
313+
DEF_MOD("rsci8_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 8, 4, 8,
314+
BUS_MSTOP(11, BIT(11))),
315+
DEF_MOD("rsci8_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 9, 4, 9,
316+
BUS_MSTOP(11, BIT(11))),
317+
DEF_MOD("rsci9_pclk", CLK_PLLCLN_DIV16, 8, 10, 4, 10,
318+
BUS_MSTOP(11, BIT(12))),
319+
DEF_MOD("rsci9_tclk", CLK_PLLCLN_DIV16, 8, 11, 4, 11,
320+
BUS_MSTOP(11, BIT(12))),
321+
DEF_MOD("rsci9_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 12, 4, 12,
322+
BUS_MSTOP(11, BIT(12))),
323+
DEF_MOD("rsci9_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 13, 4, 13,
324+
BUS_MSTOP(11, BIT(12))),
325+
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
326+
BUS_MSTOP(11, BIT(12))),
221327
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
222328
BUS_MSTOP(3, BIT(14))),
223329
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -351,6 +457,26 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
351457
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
352458
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
353459
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
460+
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
461+
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
462+
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
463+
DEF_RST(8, 4, 3, 21), /* RSCI1_TRESETN */
464+
DEF_RST(8, 5, 3, 22), /* RSCI2_PRESETN */
465+
DEF_RST(8, 6, 3, 23), /* RSCI2_TRESETN */
466+
DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */
467+
DEF_RST(8, 8, 3, 25), /* RSCI3_TRESETN */
468+
DEF_RST(8, 9, 3, 26), /* RSCI4_PRESETN */
469+
DEF_RST(8, 10, 3, 27), /* RSCI4_TRESETN */
470+
DEF_RST(8, 11, 3, 28), /* RSCI5_PRESETN */
471+
DEF_RST(8, 12, 3, 29), /* RSCI5_TRESETN */
472+
DEF_RST(8, 13, 3, 30), /* RSCI6_PRESETN */
473+
DEF_RST(8, 14, 3, 31), /* RSCI6_TRESETN */
474+
DEF_RST(8, 15, 4, 0), /* RSCI7_PRESETN */
475+
DEF_RST(9, 0, 4, 1), /* RSCI7_TRESETN */
476+
DEF_RST(9, 1, 4, 2), /* RSCI8_PRESETN */
477+
DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
478+
DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
479+
DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
354480
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
355481
DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
356482
DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */

‎drivers/clk/renesas/r9a09g056-cpg.c‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717

1818
enum clk_ids {
1919
/* Core Clock Outputs exported to DT */
20-
LAST_DT_CORE_CLK = R9A09G056_SPI_CLK_SPI,
20+
LAST_DT_CORE_CLK = R9A09G056_USB3_0_CLKCORE,
2121

2222
/* External Input Clocks */
2323
CLK_AUDIO_EXTAL,
@@ -226,6 +226,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
226226
CLK_PLLETH_DIV_125_FIX, 1, 1),
227227
DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
228228
FIXED_MOD_CONF_XSPI),
229+
DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G056_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
230+
DEF_FIXED("usb3_0_core_clk", R9A09G056_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
229231
};
230232

231233
static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
@@ -319,6 +321,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
319321
BUS_MSTOP(8, BIT(4))),
320322
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
321323
BUS_MSTOP(8, BIT(4))),
324+
DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
325+
BUS_MSTOP(7, BIT(12))),
326+
DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
327+
BUS_MSTOP(7, BIT(14))),
322328
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
323329
BUS_MSTOP(7, BIT(7))),
324330
DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
@@ -426,6 +432,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
426432
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
427433
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
428434
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
435+
DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
429436
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
430437
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
431438
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */

‎drivers/clk/renesas/r9a09g057-cpg.c‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717

1818
enum clk_ids {
1919
/* Core Clock Outputs exported to DT */
20-
LAST_DT_CORE_CLK = R9A09G057_SPI_CLK_SPI,
20+
LAST_DT_CORE_CLK = R9A09G057_USB3_1_CLKCORE,
2121

2222
/* External Input Clocks */
2323
CLK_AUDIO_EXTAL,
@@ -235,6 +235,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
235235
CLK_PLLETH_DIV_125_FIX, 1, 1),
236236
DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
237237
FIXED_MOD_CONF_XSPI),
238+
DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G057_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
239+
DEF_FIXED("usb3_0_core_clk", R9A09G057_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
240+
DEF_FIXED("usb3_1_ref_alt_clk_p", R9A09G057_USB3_1_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
241+
DEF_FIXED("usb3_1_core_clk", R9A09G057_USB3_1_CLKCORE, CLK_QEXTAL, 1, 1),
238242
};
239243

240244
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
@@ -360,6 +364,14 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
360364
BUS_MSTOP(8, BIT(4))),
361365
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
362366
BUS_MSTOP(8, BIT(4))),
367+
DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
368+
BUS_MSTOP(7, BIT(12))),
369+
DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
370+
BUS_MSTOP(7, BIT(14))),
371+
DEF_MOD("usb3_1_aclk", CLK_PLLDTY_DIV8, 11, 1, 5, 17,
372+
BUS_MSTOP(7, BIT(13))),
373+
DEF_MOD("usb3_1_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 2, 5, 18,
374+
BUS_MSTOP(7, BIT(15))),
363375
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
364376
BUS_MSTOP(7, BIT(7))),
365377
DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
@@ -501,6 +513,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
501513
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
502514
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
503515
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
516+
DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
517+
DEF_RST(10, 11, 4, 28), /* USB3_1_ARESETN */
504518
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
505519
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
506520
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */

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