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Shaoyun Liualexdeucher
Shaoyun Liu
authored and
alexdeucher
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drm/amd/amdgpu: Fix MES init sequence
When MES is been used , the set_hw_resource_1 API is required to initialize MES internal context correctly Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 13c13bd commit f81cd79

4 files changed

Lines changed: 57 additions & 60 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -143,9 +143,9 @@ struct amdgpu_mes {
143143
const struct amdgpu_mes_funcs *funcs;
144144

145145
/* mes resource_1 bo*/
146-
struct amdgpu_bo *resource_1;
147-
uint64_t resource_1_gpu_addr;
148-
void *resource_1_addr;
146+
struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES];
147+
uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES];
148+
void *resource_1_addr[AMDGPU_MAX_MES_PIPES];
149149

150150
};
151151

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -614,10 +614,11 @@ static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
614614
vf2pf_info->decode_usage = 0;
615615

616616
vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr;
617-
vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr;
618-
619-
if (adev->mes.resource_1) {
620-
vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size;
617+
if (amdgpu_sriov_is_mes_info_enable(adev)) {
618+
vf2pf_info->mes_info_addr =
619+
(uint64_t)(adev->mes.resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE);
620+
vf2pf_info->mes_info_size =
621+
adev->mes.resource_1[0]->tbo.base.size - AMDGPU_GPU_PAGE_SIZE;
621622
}
622623
vf2pf_info->checksum =
623624
amd_sriov_msg_checksum(

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c‎

Lines changed: 29 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -740,10 +740,13 @@ static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
740740
mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
741741
mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
742742
mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
743-
mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr;
744-
mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE;
745-
mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr =
746-
mes->resource_1_gpu_addr + MES11_HW_RESOURCE_1_SIZE;
743+
744+
mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0];
745+
if (amdgpu_sriov_is_mes_info_enable(mes->adev)) {
746+
mes_set_hw_res_pkt.mes_info_ctx_mc_addr =
747+
mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE;
748+
mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE;
749+
}
747750

748751
return mes_v11_0_submit_pkt_and_poll_completion(mes,
749752
&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
@@ -1381,7 +1384,7 @@ static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
13811384
static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
13821385
{
13831386
struct amdgpu_device *adev = ip_block->adev;
1384-
int pipe, r;
1387+
int pipe, r, bo_size;
13851388

13861389
adev->mes.funcs = &mes_v11_0_funcs;
13871390
adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
@@ -1416,19 +1419,21 @@ static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
14161419
if (r)
14171420
return r;
14181421

1419-
if (amdgpu_sriov_is_mes_info_enable(adev) ||
1420-
adev->gfx.enable_cleaner_shader) {
1421-
r = amdgpu_bo_create_kernel(adev,
1422-
MES11_HW_RESOURCE_1_SIZE + AMDGPU_GPU_PAGE_SIZE,
1423-
PAGE_SIZE,
1424-
AMDGPU_GEM_DOMAIN_VRAM,
1425-
&adev->mes.resource_1,
1426-
&adev->mes.resource_1_gpu_addr,
1427-
&adev->mes.resource_1_addr);
1428-
if (r) {
1429-
dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r);
1430-
return r;
1431-
}
1422+
bo_size = AMDGPU_GPU_PAGE_SIZE;
1423+
if (amdgpu_sriov_is_mes_info_enable(adev))
1424+
bo_size += MES11_HW_RESOURCE_1_SIZE;
1425+
1426+
/* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/
1427+
r = amdgpu_bo_create_kernel(adev,
1428+
bo_size,
1429+
PAGE_SIZE,
1430+
AMDGPU_GEM_DOMAIN_VRAM,
1431+
&adev->mes.resource_1[0],
1432+
&adev->mes.resource_1_gpu_addr[0],
1433+
&adev->mes.resource_1_addr[0]);
1434+
if (r) {
1435+
dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r);
1436+
return r;
14321437
}
14331438

14341439
return 0;
@@ -1439,11 +1444,8 @@ static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)
14391444
struct amdgpu_device *adev = ip_block->adev;
14401445
int pipe;
14411446

1442-
if (amdgpu_sriov_is_mes_info_enable(adev) ||
1443-
adev->gfx.enable_cleaner_shader) {
1444-
amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
1445-
&adev->mes.resource_1_addr);
1446-
}
1447+
amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0],
1448+
&adev->mes.resource_1_addr[0]);
14471449

14481450
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
14491451
kfree(adev->mes.mqd_backup[pipe]);
@@ -1632,13 +1634,10 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
16321634
if (r)
16331635
goto failure;
16341636

1635-
if (amdgpu_sriov_is_mes_info_enable(adev) ||
1636-
adev->gfx.enable_cleaner_shader) {
1637-
r = mes_v11_0_set_hw_resources_1(&adev->mes);
1638-
if (r) {
1639-
DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
1640-
goto failure;
1641-
}
1637+
r = mes_v11_0_set_hw_resources_1(&adev->mes);
1638+
if (r) {
1639+
DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
1640+
goto failure;
16421641
}
16431642

16441643
r = mes_v11_0_query_sched_status(&adev->mes);

‎drivers/gpu/drm/amd/amdgpu/mes_v12_0.c‎

Lines changed: 20 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -687,7 +687,7 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
687687
mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
688688
mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
689689
mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr =
690-
mes->resource_1_gpu_addr;
690+
mes->resource_1_gpu_addr[pipe];
691691

692692
return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
693693
&mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
@@ -1519,23 +1519,22 @@ static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
15191519
if (r)
15201520
return r;
15211521

1522-
if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1522+
if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) {
15231523
r = mes_v12_0_kiq_ring_init(adev);
1524-
else
1524+
}
1525+
else {
15251526
r = mes_v12_0_ring_init(adev, pipe);
1526-
if (r)
1527-
return r;
1528-
}
1529-
1530-
if (adev->enable_uni_mes) {
1531-
r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1532-
AMDGPU_GEM_DOMAIN_VRAM,
1533-
&adev->mes.resource_1,
1534-
&adev->mes.resource_1_gpu_addr,
1535-
&adev->mes.resource_1_addr);
1536-
if (r) {
1537-
dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r);
1538-
return r;
1527+
if (r)
1528+
return r;
1529+
r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1530+
AMDGPU_GEM_DOMAIN_VRAM,
1531+
&adev->mes.resource_1[pipe],
1532+
&adev->mes.resource_1_gpu_addr[pipe],
1533+
&adev->mes.resource_1_addr[pipe]);
1534+
if (r) {
1535+
dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe);
1536+
return r;
1537+
}
15391538
}
15401539
}
15411540

@@ -1547,12 +1546,11 @@ static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
15471546
struct amdgpu_device *adev = ip_block->adev;
15481547
int pipe;
15491548

1550-
if (adev->enable_uni_mes)
1551-
amdgpu_bo_free_kernel(&adev->mes.resource_1,
1552-
&adev->mes.resource_1_gpu_addr,
1553-
&adev->mes.resource_1_addr);
1554-
15551549
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1550+
amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe],
1551+
&adev->mes.resource_1_gpu_addr[pipe],
1552+
&adev->mes.resource_1_addr[pipe]);
1553+
15561554
kfree(adev->mes.mqd_backup[pipe]);
15571555

15581556
amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
@@ -1751,8 +1749,7 @@ static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
17511749
if (r)
17521750
goto failure;
17531751

1754-
if (adev->enable_uni_mes)
1755-
mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1752+
mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);
17561753

17571754
mes_v12_0_init_aggregated_doorbell(&adev->mes);
17581755

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