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6 | 6 | #include <dt-bindings/pinctrl/rockchip.h> |
7 | 7 | #include <dt-bindings/clock/rk3036-cru.h> |
8 | 8 | #include <dt-bindings/soc/rockchip,boot-mode.h> |
| 9 | +#include <dt-bindings/power/rk3036-power.h> |
9 | 10 |
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10 | 11 | / { |
11 | 12 | #address-cells = <1>; |
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111 | 112 | assigned-clock-rates = <100000000>; |
112 | 113 | clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; |
113 | 114 | clock-names = "bus", "core"; |
| 115 | + power-domains = <&power RK3036_PD_GPU>; |
114 | 116 | resets = <&cru SRST_GPU>; |
115 | 117 | status = "disabled"; |
116 | 118 | }; |
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124 | 126 | resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; |
125 | 127 | reset-names = "axi", "ahb", "dclk"; |
126 | 128 | iommus = <&vop_mmu>; |
| 129 | + power-domains = <&power RK3036_PD_VIO>; |
127 | 130 | status = "disabled"; |
128 | 131 |
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129 | 132 | vop_out: port { |
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140 | 143 | compatible = "rockchip,iommu"; |
141 | 144 | reg = <0x10118300 0x100>; |
142 | 145 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
143 | | - interrupt-names = "vop_mmu"; |
144 | 146 | clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; |
145 | 147 | clock-names = "aclk", "iface"; |
| 148 | + power-domains = <&power RK3036_PD_VIO>; |
146 | 149 | #iommu-cells = <0>; |
147 | 150 | status = "disabled"; |
148 | 151 | }; |
149 | 152 |
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| 153 | + qos_gpu: qos@1012d000 { |
| 154 | + compatible = "rockchip,rk3036-qos", "syscon"; |
| 155 | + reg = <0x1012d000 0x20>; |
| 156 | + }; |
| 157 | + |
| 158 | + qos_vpu: qos@1012e000 { |
| 159 | + compatible = "rockchip,rk3036-qos", "syscon"; |
| 160 | + reg = <0x1012e000 0x20>; |
| 161 | + }; |
| 162 | + |
| 163 | + qos_vio: qos@1012f000 { |
| 164 | + compatible = "rockchip,rk3036-qos", "syscon"; |
| 165 | + reg = <0x1012f000 0x20>; |
| 166 | + }; |
| 167 | + |
150 | 168 | gic: interrupt-controller@10139000 { |
151 | 169 | compatible = "arm,gic-400"; |
152 | 170 | interrupt-controller; |
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302 | 320 | compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; |
303 | 321 | reg = <0x20008000 0x1000>; |
304 | 322 |
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| 323 | + power: power-controller { |
| 324 | + compatible = "rockchip,rk3036-power-controller"; |
| 325 | + #power-domain-cells = <1>; |
| 326 | + #address-cells = <1>; |
| 327 | + #size-cells = <0>; |
| 328 | + |
| 329 | + power-domain@RK3036_PD_VIO { |
| 330 | + reg = <RK3036_PD_VIO>; |
| 331 | + clocks = <&cru ACLK_LCDC>, |
| 332 | + <&cru HCLK_LCDC>, |
| 333 | + <&cru SCLK_LCDC>; |
| 334 | + pm_qos = <&qos_vio>; |
| 335 | + #power-domain-cells = <0>; |
| 336 | + }; |
| 337 | + |
| 338 | + power-domain@RK3036_PD_VPU { |
| 339 | + reg = <RK3036_PD_VPU>; |
| 340 | + clocks = <&cru ACLK_VCODEC>, |
| 341 | + <&cru HCLK_VCODEC>; |
| 342 | + pm_qos = <&qos_vpu>; |
| 343 | + #power-domain-cells = <0>; |
| 344 | + }; |
| 345 | + |
| 346 | + power-domain@RK3036_PD_GPU { |
| 347 | + reg = <RK3036_PD_GPU>; |
| 348 | + clocks = <&cru SCLK_GPU>; |
| 349 | + pm_qos = <&qos_gpu>; |
| 350 | + #power-domain-cells = <0>; |
| 351 | + }; |
| 352 | + }; |
| 353 | + |
305 | 354 | reboot-mode { |
306 | 355 | compatible = "syscon-reboot-mode"; |
307 | 356 | offset = <0x1d8>; |
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