3030#define REG_TOK_RDATA1 0x1c
3131
3232/* Control register fields */
33- #define REG_CTRL_START BIT(0)
34- #define REG_CTRL_ACK_IGNORE BIT(1)
35- #define REG_CTRL_STATUS BIT(2)
36- #define REG_CTRL_ERROR BIT(3)
37- #define REG_CTRL_CLKDIV GENMASK(21, 12)
38- #define REG_CTRL_CLKDIVEXT GENMASK(29, 28)
39-
40- #define REG_SLV_ADDR GENMASK(7, 0)
41- #define REG_SLV_SDA_FILTER GENMASK(10, 8)
42- #define REG_SLV_SCL_FILTER GENMASK(13, 11)
43- #define REG_SLV_SCL_LOW GENMASK(27, 16)
44- #define REG_SLV_SCL_LOW_EN BIT(28)
33+ #define REG_CTRL_START BIT(0)
34+ #define REG_CTRL_ACK_IGNORE BIT(1)
35+ #define REG_CTRL_STATUS BIT(2)
36+ #define REG_CTRL_ERROR BIT(3)
37+ #define REG_CTRL_CLKDIV_SHIFT 12
38+ #define REG_CTRL_CLKDIV_MASK GENMASK(21, REG_CTRL_CLKDIV_SHIFT)
39+ #define REG_CTRL_CLKDIVEXT_SHIFT 28
40+ #define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, REG_CTRL_CLKDIVEXT_SHIFT)
41+
42+ #define REG_SLV_ADDR_MASK GENMASK(7, 0)
43+ #define REG_SLV_SDA_FILTER_MASK GENMASK(10, 8)
44+ #define REG_SLV_SCL_FILTER_MASK GENMASK(13, 11)
45+ #define REG_SLV_SCL_LOW_SHIFT 16
46+ #define REG_SLV_SCL_LOW_MASK GENMASK(27, REG_SLV_SCL_LOW_SHIFT)
47+ #define REG_SLV_SCL_LOW_EN BIT(28)
4548
4649#define I2C_TIMEOUT_MS 500
4750#define FILTER_DELAY 15
@@ -62,10 +65,6 @@ enum {
6265 STATE_WRITE ,
6366};
6467
65- struct meson_i2c_data {
66- unsigned char div_factor ;
67- };
68-
6968/**
7069 * struct meson_i2c - Meson I2C device private data
7170 *
@@ -83,7 +82,7 @@ struct meson_i2c_data {
8382 * @done: Completion used to wait for transfer termination
8483 * @tokens: Sequence of tokens to be written to the device
8584 * @num_tokens: Number of tokens
86- * @data: Pointer to the controlller 's platform data
85+ * @data: Pointer to the controller 's platform data
8786 */
8887struct meson_i2c {
8988 struct i2c_adapter adap ;
@@ -106,6 +105,10 @@ struct meson_i2c {
106105 const struct meson_i2c_data * data ;
107106};
108107
108+ struct meson_i2c_data {
109+ void (* set_clk_div )(struct meson_i2c * i2c , unsigned int freq );
110+ };
111+
109112static void meson_i2c_set_mask (struct meson_i2c * i2c , int reg , u32 mask ,
110113 u32 val )
111114{
@@ -134,26 +137,74 @@ static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
134137 i2c -> num_tokens ++ ;
135138}
136139
137- static void meson_i2c_set_clk_div (struct meson_i2c * i2c , unsigned int freq )
140+ static void meson_gxbb_axg_i2c_set_clk_div (struct meson_i2c * i2c , unsigned int freq )
141+ {
142+ unsigned long clk_rate = clk_get_rate (i2c -> clk );
143+ unsigned int div_h , div_l ;
144+
145+ /* According to I2C-BUS Spec 2.1, in FAST-MODE, the minimum LOW period is 1.3uS, and
146+ * minimum HIGH is least 0.6us.
147+ * For 400000 freq, the period is 2.5us. To keep within the specs, give 40% of period to
148+ * HIGH and 60% to LOW. This means HIGH at 1.0us and LOW 1.5us.
149+ * The same applies for Fast-mode plus, where LOW is 0.5us and HIGH is 0.26us.
150+ * Duty = H/(H + L) = 2/5
151+ */
152+ if (freq <= I2C_MAX_STANDARD_MODE_FREQ ) {
153+ div_h = DIV_ROUND_UP (clk_rate , freq );
154+ div_l = DIV_ROUND_UP (div_h , 4 );
155+ div_h = DIV_ROUND_UP (div_h , 2 ) - FILTER_DELAY ;
156+ } else {
157+ div_h = DIV_ROUND_UP (clk_rate * 2 , freq * 5 ) - FILTER_DELAY ;
158+ div_l = DIV_ROUND_UP (clk_rate * 3 , freq * 5 * 2 );
159+ }
160+
161+ /* clock divider has 12 bits */
162+ if (div_h > GENMASK (11 , 0 )) {
163+ dev_err (i2c -> dev , "requested bus frequency too low\n" );
164+ div_h = GENMASK (11 , 0 );
165+ }
166+ if (div_l > GENMASK (11 , 0 )) {
167+ dev_err (i2c -> dev , "requested bus frequency too low\n" );
168+ div_l = GENMASK (11 , 0 );
169+ }
170+
171+ meson_i2c_set_mask (i2c , REG_CTRL , REG_CTRL_CLKDIV_MASK ,
172+ FIELD_PREP (REG_CTRL_CLKDIV_MASK , div_h & GENMASK (9 , 0 )));
173+
174+ meson_i2c_set_mask (i2c , REG_CTRL , REG_CTRL_CLKDIVEXT_MASK ,
175+ FIELD_PREP (REG_CTRL_CLKDIVEXT_MASK , div_h >> 10 ));
176+
177+ /* set SCL low delay */
178+ meson_i2c_set_mask (i2c , REG_SLAVE_ADDR , REG_SLV_SCL_LOW_MASK ,
179+ FIELD_PREP (REG_SLV_SCL_LOW_MASK , div_l ));
180+
181+ /* Enable HIGH/LOW mode */
182+ meson_i2c_set_mask (i2c , REG_SLAVE_ADDR , REG_SLV_SCL_LOW_EN , REG_SLV_SCL_LOW_EN );
183+
184+ dev_dbg (i2c -> dev , "%s: clk %lu, freq %u, divh %u, divl %u\n" , __func__ ,
185+ clk_rate , freq , div_h , div_l );
186+ }
187+
188+ static void meson6_i2c_set_clk_div (struct meson_i2c * i2c , unsigned int freq )
138189{
139190 unsigned long clk_rate = clk_get_rate (i2c -> clk );
140191 unsigned int div ;
141192
142193 div = DIV_ROUND_UP (clk_rate , freq );
143194 div -= FILTER_DELAY ;
144- div = DIV_ROUND_UP (div , i2c -> data -> div_factor );
195+ div = DIV_ROUND_UP (div , 4 );
145196
146197 /* clock divider has 12 bits */
147198 if (div > GENMASK (11 , 0 )) {
148199 dev_err (i2c -> dev , "requested bus frequency too low\n" );
149200 div = GENMASK (11 , 0 );
150201 }
151202
152- meson_i2c_set_mask (i2c , REG_CTRL , REG_CTRL_CLKDIV ,
153- FIELD_PREP (REG_CTRL_CLKDIV , div & GENMASK (9 , 0 )));
203+ meson_i2c_set_mask (i2c , REG_CTRL , REG_CTRL_CLKDIV_MASK ,
204+ FIELD_PREP (REG_CTRL_CLKDIV_MASK , div & GENMASK (9 , 0 )));
154205
155- meson_i2c_set_mask (i2c , REG_CTRL , REG_CTRL_CLKDIVEXT ,
156- FIELD_PREP (REG_CTRL_CLKDIVEXT , div >> 10 ));
206+ meson_i2c_set_mask (i2c , REG_CTRL , REG_CTRL_CLKDIVEXT_MASK ,
207+ FIELD_PREP (REG_CTRL_CLKDIVEXT_MASK , div >> 10 ));
157208
158209 /* Disable HIGH/LOW mode */
159210 meson_i2c_set_mask (i2c , REG_SLAVE_ADDR , REG_SLV_SCL_LOW_EN , 0 );
@@ -292,8 +343,8 @@ static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
292343 TOKEN_SLAVE_ADDR_WRITE ;
293344
294345
295- meson_i2c_set_mask (i2c , REG_SLAVE_ADDR , REG_SLV_ADDR ,
296- FIELD_PREP (REG_SLV_ADDR , msg -> addr << 1 ));
346+ meson_i2c_set_mask (i2c , REG_SLAVE_ADDR , REG_SLV_ADDR_MASK ,
347+ FIELD_PREP (REG_SLV_ADDR_MASK , msg -> addr << 1 ));
297348
298349 meson_i2c_add_token (i2c , TOKEN_START );
299350 meson_i2c_add_token (i2c , token );
@@ -467,9 +518,13 @@ static int meson_i2c_probe(struct platform_device *pdev)
467518
468519 /* Disable filtering */
469520 meson_i2c_set_mask (i2c , REG_SLAVE_ADDR ,
470- REG_SLV_SDA_FILTER | REG_SLV_SCL_FILTER , 0 );
521+ REG_SLV_SDA_FILTER_MASK | REG_SLV_SCL_FILTER_MASK , 0 );
471522
472- meson_i2c_set_clk_div (i2c , timings .bus_freq_hz );
523+ if (!i2c -> data -> set_clk_div ) {
524+ clk_disable_unprepare (i2c -> clk );
525+ return - EINVAL ;
526+ }
527+ i2c -> data -> set_clk_div (i2c , timings .bus_freq_hz );
473528
474529 ret = i2c_add_adapter (& i2c -> adap );
475530 if (ret < 0 ) {
@@ -491,15 +546,15 @@ static int meson_i2c_remove(struct platform_device *pdev)
491546}
492547
493548static const struct meson_i2c_data i2c_meson6_data = {
494- .div_factor = 4 ,
549+ .set_clk_div = meson6_i2c_set_clk_div ,
495550};
496551
497552static const struct meson_i2c_data i2c_gxbb_data = {
498- .div_factor = 4 ,
553+ .set_clk_div = meson_gxbb_axg_i2c_set_clk_div ,
499554};
500555
501556static const struct meson_i2c_data i2c_axg_data = {
502- .div_factor = 3 ,
557+ .set_clk_div = meson_gxbb_axg_i2c_set_clk_div ,
503558};
504559
505560static const struct of_device_id meson_i2c_match [] = {
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