4141#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
4242 ASPM_STATE_L1SS)
4343
44- struct aspm_latency {
45- u32 l0s ; /* L0s latency (nsec) */
46- u32 l1 ; /* L1 latency (nsec) */
47- };
48-
4944struct pcie_link_state {
5045 struct pci_dev * pdev ; /* Upstream component of the Link */
5146 struct pci_dev * downstream ; /* Downstream component, function 0 */
@@ -384,9 +379,9 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
384379static void pcie_aspm_check_latency (struct pci_dev * endpoint )
385380{
386381 u32 latency , encoding , lnkcap_up , lnkcap_dw ;
387- u32 l1_switch_latency = 0 ;
388- struct aspm_latency latency_up , latency_dw ;
389- struct aspm_latency * acceptable ;
382+ u32 l1_switch_latency = 0 , latency_up_l0s ;
383+ u32 latency_up_l1 , latency_dw_l0s , latency_dw_l1 ;
384+ u32 acceptable_l0s , acceptable_l1 ;
390385 struct pcie_link_state * link ;
391386
392387 /* Device not in D0 doesn't need latency check */
@@ -398,11 +393,11 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
398393
399394 /* Calculate endpoint L0s acceptable latency */
400395 encoding = (endpoint -> devcap & PCI_EXP_DEVCAP_L0S ) >> 6 ;
401- acceptable -> l0s = calc_l0s_acceptable (encoding );
396+ acceptable_l0s = calc_l0s_acceptable (encoding );
402397
403398 /* Calculate endpoint L1 acceptable latency */
404399 encoding = (endpoint -> devcap & PCI_EXP_DEVCAP_L1 ) >> 9 ;
405- acceptable -> l1 = calc_l1_acceptable (encoding );
400+ acceptable_l1 = calc_l1_acceptable (encoding );
406401
407402 while (link ) {
408403 struct pci_dev * dev = pci_function_0 (link -> pdev -> subordinate );
@@ -412,19 +407,19 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
412407 & lnkcap_up );
413408 pcie_capability_read_dword (dev , PCI_EXP_LNKCAP ,
414409 & lnkcap_dw );
415- latency_up . l0s = calc_l0s_latency (lnkcap_up );
416- latency_up . l1 = calc_l1_latency (lnkcap_up );
417- latency_dw . l0s = calc_l0s_latency (lnkcap_dw );
418- latency_dw . l1 = calc_l1_latency (lnkcap_dw );
410+ latency_up_l0s = calc_l0s_latency (lnkcap_up );
411+ latency_up_l1 = calc_l1_latency (lnkcap_up );
412+ latency_dw_l0s = calc_l0s_latency (lnkcap_dw );
413+ latency_dw_l1 = calc_l1_latency (lnkcap_dw );
419414
420415 /* Check upstream direction L0s latency */
421416 if ((link -> aspm_capable & ASPM_STATE_L0S_UP ) &&
422- (latency_up . l0s > acceptable -> l0s ))
417+ (latency_up_l0s > acceptable_l0s ))
423418 link -> aspm_capable &= ~ASPM_STATE_L0S_UP ;
424419
425420 /* Check downstream direction L0s latency */
426421 if ((link -> aspm_capable & ASPM_STATE_L0S_DW ) &&
427- (latency_dw . l0s > acceptable -> l0s ))
422+ (latency_dw_l0s > acceptable_l0s ))
428423 link -> aspm_capable &= ~ASPM_STATE_L0S_DW ;
429424 /*
430425 * Check L1 latency.
@@ -439,9 +434,9 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
439434 * L1 exit latencies advertised by a device include L1
440435 * substate latencies (and hence do not do any check).
441436 */
442- latency = max_t (u32 , latency_up . l1 , latency_dw . l1 );
437+ latency = max_t (u32 , latency_up_l1 , latency_dw_l1 );
443438 if ((link -> aspm_capable & ASPM_STATE_L1 ) &&
444- (latency + l1_switch_latency > acceptable -> l1 ))
439+ (latency + l1_switch_latency > acceptable_l1 ))
445440 link -> aspm_capable &= ~ASPM_STATE_L1 ;
446441 l1_switch_latency += 1000 ;
447442
@@ -668,7 +663,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
668663
669664 /* Get and check endpoint acceptable latencies */
670665 list_for_each_entry (child , & linkbus -> devices , bus_list ) {
671-
672666 if (pci_pcie_type (child ) != PCI_EXP_TYPE_ENDPOINT &&
673667 pci_pcie_type (child ) != PCI_EXP_TYPE_LEG_END )
674668 continue ;
0 commit comments