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Kenneth Fengalexdeucher
Kenneth Feng
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alexdeucher
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drm/amd/swsmu: add smu14 ip support
Add initial swSMU support for smu 14 series ASIC. v2: rebase (Alex) Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 577cbed commit fa62c03

2 files changed

Lines changed: 54 additions & 26 deletions

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‎drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,8 @@
3939
#define MP1_SRAM 0x03c00004
4040

4141
/* address block */
42-
#define smnMP1_FIRMWARE_FLAGS 0x3010028
42+
#define smnMP1_FIRMWARE_FLAGS_14_0_0 0x3010028
43+
#define smnMP1_FIRMWARE_FLAGS 0x3010024
4344
#define smnMP1_PUB_CTRL 0x3010d10
4445

4546
#define MAX_DPM_LEVELS 16

‎drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c‎

Lines changed: 52 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,13 @@
3838
#include "amdgpu_ras.h"
3939
#include "smu_cmn.h"
4040

41-
#include "asic_reg/mp/mp_14_0_0_offset.h"
42-
#include "asic_reg/mp/mp_14_0_0_sh_mask.h"
41+
#include "asic_reg/mp/mp_14_0_2_offset.h"
42+
#include "asic_reg/mp/mp_14_0_2_sh_mask.h"
43+
44+
#define regMP1_SMN_IH_SW_INT_mp1_14_0_0 0x0341
45+
#define regMP1_SMN_IH_SW_INT_mp1_14_0_0_BASE_IDX 0
46+
#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0 0x0342
47+
#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX 0
4348

4449
/*
4550
* DO NOT use these for err/warn/info/debug messages.
@@ -52,14 +57,15 @@
5257
#undef pr_debug
5358

5459
MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin");
60+
MODULE_FIRMWARE("amdgpu/smu_14_0_3.bin");
5561

5662
#define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
5763

5864
int smu_v14_0_init_microcode(struct smu_context *smu)
5965
{
6066
struct amdgpu_device *adev = smu->adev;
6167
char fw_name[30];
62-
char ucode_prefix[15];
68+
char ucode_prefix[30];
6369
int err = 0;
6470
const struct smc_firmware_header_v1_0 *hdr;
6571
const struct common_firmware_header *header;
@@ -106,7 +112,6 @@ void smu_v14_0_fini_microcode(struct smu_context *smu)
106112

107113
int smu_v14_0_load_microcode(struct smu_context *smu)
108114
{
109-
#if 0
110115
struct amdgpu_device *adev = smu->adev;
111116
const uint32_t *src;
112117
const struct smc_firmware_header_v1_0 *hdr;
@@ -131,8 +136,12 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
131136
1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
132137

133138
for (i = 0; i < adev->usec_timeout; i++) {
134-
mp1_fw_flags = RREG32_PCIE(MP1_Public |
135-
(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
139+
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
140+
mp1_fw_flags = RREG32_PCIE(MP1_Public |
141+
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
142+
else
143+
mp1_fw_flags = RREG32_PCIE(MP1_Public |
144+
(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
136145
if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
137146
MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
138147
break;
@@ -142,9 +151,7 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
142151
if (i == adev->usec_timeout)
143152
return -ETIME;
144153

145-
#endif
146154
return 0;
147-
148155
}
149156

150157
int smu_v14_0_init_pptable_microcode(struct smu_context *smu)
@@ -198,7 +205,11 @@ int smu_v14_0_check_fw_status(struct smu_context *smu)
198205
struct amdgpu_device *adev = smu->adev;
199206
uint32_t mp1_fw_flags;
200207

201-
mp1_fw_flags = RREG32_PCIE(MP1_Public |
208+
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
209+
mp1_fw_flags = RREG32_PCIE(MP1_Public |
210+
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
211+
else
212+
mp1_fw_flags = RREG32_PCIE(MP1_Public |
202213
(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
203214

204215
if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
@@ -227,16 +238,15 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
227238
adev->pm.fw_version = smu_version;
228239

229240
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
230-
case IP_VERSION(14, 0, 2):
231-
smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
232-
break;
233241
case IP_VERSION(14, 0, 0):
234242
smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
235243
break;
236244
case IP_VERSION(14, 0, 1):
237245
smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_1;
238246
break;
239-
247+
case IP_VERSION(14, 0, 2):
248+
smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
249+
break;
240250
default:
241251
dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
242252
amdgpu_ip_version(adev, MP1_HWIP, 0));
@@ -738,9 +748,9 @@ int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
738748
struct amdgpu_device *adev = smu->adev;
739749

740750
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
741-
case IP_VERSION(14, 0, 2):
742751
case IP_VERSION(14, 0, 0):
743752
case IP_VERSION(14, 0, 1):
753+
case IP_VERSION(14, 0, 2):
744754
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
745755
return 0;
746756
if (enable)
@@ -841,24 +851,41 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
841851
// TODO
842852

843853
/* For MP1 SW irqs */
844-
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
845-
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
846-
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
854+
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
855+
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
856+
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
857+
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
858+
} else {
859+
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
860+
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
861+
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
862+
}
847863

848864
break;
849865
case AMDGPU_IRQ_STATE_ENABLE:
850866
/* For THM irqs */
851867
// TODO
852868

853869
/* For MP1 SW irqs */
854-
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
855-
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
856-
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
857-
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
858-
859-
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
860-
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
861-
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
870+
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
871+
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
872+
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
873+
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
874+
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0, val);
875+
876+
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
877+
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
878+
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
879+
} else {
880+
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
881+
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
882+
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
883+
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
884+
885+
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
886+
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
887+
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
888+
}
862889

863890
break;
864891
default:

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