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Li Maalexdeucher
Li Ma
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alexdeucher
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drm/amdgpu: fix missing stuff in NBIO v7.11
add get_clockgating_state, update_medium_grain_light_sleep and update_medium_grain_clock_gating in nbio_v7_11_funcs v1: add missing funcs in nbio_v7_11.c v2: modify the if condition and add spport for nbio v7.11 clockgating. Signed-off-by: Li Ma <li.ma@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 66d64e4 commit fa9dd7a

4 files changed

Lines changed: 97 additions & 1 deletion

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‎drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -272,6 +272,81 @@ static void nbio_v7_11_init_registers(struct amdgpu_device *adev)
272272
*/
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}
274274

275+
static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev,
276+
bool enable)
277+
{
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uint32_t def, data;
279+
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if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
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return;
282+
283+
def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);
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if (enable) {
285+
data |= (BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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} else {
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data &= ~(BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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}
299+
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if (def != data)
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WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL, data);
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}
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static void nbio_v7_11_update_medium_grain_light_sleep(struct amdgpu_device *adev,
305+
bool enable)
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{
307+
uint32_t def, data;
308+
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if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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return;
311+
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def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);
313+
if (enable)
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data |= BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
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else
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data &= ~BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
317+
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if (def != data)
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WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2, data);
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321+
def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1);
322+
if (enable) {
323+
data |= (BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
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} else {
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data &= ~(BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
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BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
328+
}
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330+
if (def != data)
331+
WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1, data);
332+
}
333+
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static void nbio_v7_11_get_clockgating_state(struct amdgpu_device *adev,
335+
u64 *flags)
336+
{
337+
uint32_t data;
338+
339+
/* AMD_CG_SUPPORT_BIF_MGCG */
340+
data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);
341+
if (data & BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
342+
*flags |= AMD_CG_SUPPORT_BIF_MGCG;
343+
344+
/* AMD_CG_SUPPORT_BIF_LS */
345+
data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);
346+
if (data & BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
347+
*flags |= AMD_CG_SUPPORT_BIF_LS;
348+
}
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const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
276351
.get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset,
277352
.get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset,
@@ -288,6 +363,9 @@ const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
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.enable_doorbell_aperture = nbio_v7_11_enable_doorbell_aperture,
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.enable_doorbell_selfring_aperture = nbio_v7_11_enable_doorbell_selfring_aperture,
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.ih_doorbell_range = nbio_v7_11_ih_doorbell_range,
366+
.update_medium_grain_clock_gating = nbio_v7_11_update_medium_grain_clock_gating,
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.update_medium_grain_light_sleep = nbio_v7_11_update_medium_grain_light_sleep,
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.get_clockgating_state = nbio_v7_11_get_clockgating_state,
291369
.ih_control = nbio_v7_11_ih_control,
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.init_registers = nbio_v7_11_init_registers,
293371
.remap_hdp_registers = nbio_v7_11_remap_hdp_registers,

‎drivers/gpu/drm/amd/amdgpu/soc21.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -863,6 +863,7 @@ static int soc21_common_set_clockgating_state(void *handle,
863863
case IP_VERSION(4, 3, 0):
864864
case IP_VERSION(4, 3, 1):
865865
case IP_VERSION(7, 7, 0):
866+
case IP_VERSION(7, 11, 0):
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adev->nbio.funcs->update_medium_grain_clock_gating(adev,
867868
state == AMD_CG_STATE_GATE);
868869
adev->nbio.funcs->update_medium_grain_light_sleep(adev,

‎drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -775,6 +775,12 @@
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#define regPCIE_USB4_ERR_CNTL5_BASE_IDX 5
776776
#define regPCIE_USB4_LC_CNTL1 0x420179
777777
#define regPCIE_USB4_LC_CNTL1_BASE_IDX 5
778+
#define regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL 0x420118
779+
#define regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL_BASE_IDX 5
780+
#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2 0x42001c
781+
#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2_BASE_IDX 5
782+
#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 0x420187
783+
#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
778784

779785

780786
// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp

‎drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24634,7 +24634,18 @@
2463424634
//PCIE_USB4_LC_CNTL1
2463524635
#define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE__SHIFT 0x0
2463624636
#define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE_MASK 0x00000001L
24637-
24637+
//BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL
24638+
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L
24639+
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L
24640+
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L
24641+
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L
24642+
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L
24643+
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L
24644+
//BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2
24645+
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L
24646+
//BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1
24647+
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
24648+
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
2463824649

2463924650
// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
2464024651
//BIF_CFG_DEV0_RC0_VENDOR_ID

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