@@ -114,6 +114,7 @@ struct mchp_pdmc {
114114 struct clk * gclk ;
115115 u32 pdmcen ;
116116 u32 suspend_irq ;
117+ u32 startup_delay_us ;
117118 int mic_no ;
118119 int sinc_order ;
119120 bool audio_filter_en ;
@@ -425,6 +426,7 @@ static const struct snd_soc_component_driver mchp_pdmc_dai_component = {
425426 .open = & mchp_pdmc_open ,
426427 .close = & mchp_pdmc_close ,
427428 .legacy_dai_naming = 1 ,
429+ .start_dma_last = 1 ,
428430};
429431
430432static const unsigned int mchp_pdmc_1mic [] = {1 };
@@ -632,6 +634,29 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream,
632634 return 0 ;
633635}
634636
637+ static void mchp_pdmc_noise_filter_workaround (struct mchp_pdmc * dd )
638+ {
639+ u32 tmp , steps = 16 ;
640+
641+ /*
642+ * PDMC doesn't wait for microphones' startup time thus the acquisition
643+ * may start before the microphones are ready leading to poc noises at
644+ * the beginning of capture. To avoid this, we need to wait 50ms (in
645+ * normal startup procedure) or 150 ms (worst case after resume from sleep
646+ * states) after microphones are enabled and then clear the FIFOs (by
647+ * reading the RHR 16 times) and possible interrupts before continuing.
648+ * Also, for this to work the DMA needs to be started after interrupts
649+ * are enabled.
650+ */
651+ usleep_range (dd -> startup_delay_us , dd -> startup_delay_us + 5 );
652+
653+ while (steps -- )
654+ regmap_read (dd -> regmap , MCHP_PDMC_RHR , & tmp );
655+
656+ /* Clear interrupts. */
657+ regmap_read (dd -> regmap , MCHP_PDMC_ISR , & tmp );
658+ }
659+
635660static int mchp_pdmc_trigger (struct snd_pcm_substream * substream ,
636661 int cmd , struct snd_soc_dai * dai )
637662{
@@ -644,15 +669,17 @@ static int mchp_pdmc_trigger(struct snd_pcm_substream *substream,
644669 switch (cmd ) {
645670 case SNDRV_PCM_TRIGGER_RESUME :
646671 case SNDRV_PCM_TRIGGER_START :
647- /* Enable overrun and underrun error interrupts */
648- regmap_write (dd -> regmap , MCHP_PDMC_IER , dd -> suspend_irq |
649- MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR );
650- dd -> suspend_irq = 0 ;
651- fallthrough ;
652672 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE :
653673 snd_soc_component_update_bits (cpu , MCHP_PDMC_MR ,
654674 MCHP_PDMC_MR_PDMCEN_MASK ,
655675 dd -> pdmcen );
676+
677+ mchp_pdmc_noise_filter_workaround (dd );
678+
679+ /* Enable interrupts. */
680+ regmap_write (dd -> regmap , MCHP_PDMC_IER , dd -> suspend_irq |
681+ MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR );
682+ dd -> suspend_irq = 0 ;
656683 break ;
657684 case SNDRV_PCM_TRIGGER_SUSPEND :
658685 regmap_read (dd -> regmap , MCHP_PDMC_IMR , & dd -> suspend_irq );
@@ -796,6 +823,7 @@ static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg)
796823 case MCHP_PDMC_CFGR :
797824 case MCHP_PDMC_IMR :
798825 case MCHP_PDMC_ISR :
826+ case MCHP_PDMC_RHR :
799827 case MCHP_PDMC_VER :
800828 return true;
801829 default :
@@ -817,6 +845,17 @@ static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg)
817845 }
818846}
819847
848+ static bool mchp_pdmc_volatile_reg (struct device * dev , unsigned int reg )
849+ {
850+ switch (reg ) {
851+ case MCHP_PDMC_ISR :
852+ case MCHP_PDMC_RHR :
853+ return true;
854+ default :
855+ return false;
856+ }
857+ }
858+
820859static bool mchp_pdmc_precious_reg (struct device * dev , unsigned int reg )
821860{
822861 switch (reg ) {
@@ -836,6 +875,7 @@ static const struct regmap_config mchp_pdmc_regmap_config = {
836875 .readable_reg = mchp_pdmc_readable_reg ,
837876 .writeable_reg = mchp_pdmc_writeable_reg ,
838877 .precious_reg = mchp_pdmc_precious_reg ,
878+ .volatile_reg = mchp_pdmc_volatile_reg ,
839879 .cache_type = REGCACHE_FLAT ,
840880};
841881
@@ -918,6 +958,9 @@ static int mchp_pdmc_dt_init(struct mchp_pdmc *dd)
918958 dd -> channel_mic_map [i ].clk_edge = edge ;
919959 }
920960
961+ dd -> startup_delay_us = 150000 ;
962+ of_property_read_u32 (np , "microchip,startup-delay-us" , & dd -> startup_delay_us );
963+
921964 return 0 ;
922965}
923966
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