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alexdeucheralexdeucher
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drm/amdgpu/gfx12: don't read registers in mqd init
Just use the default values. There's not need to get the value from hardware and it could cause problems if we do that at runtime and gfxoff is active. Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent e27b36e commit fc3c139

1 file changed

Lines changed: 33 additions & 15 deletions

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‎drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c‎

Lines changed: 33 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,24 @@
5050

5151
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
5252

53+
#define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
54+
#define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
55+
#define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
56+
#define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
57+
#define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000
58+
#define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
59+
#define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000
60+
61+
#define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
62+
#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
63+
#define regCP_MQD_CONTROL_DEFAULT 0x00000100
64+
#define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
65+
#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
66+
#define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000
67+
#define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501
68+
#define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000
69+
70+
5371
MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
5472
MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
5573
MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin");
@@ -2891,25 +2909,25 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
28912909
mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
28922910

28932911
/* set up mqd control */
2894-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
2912+
tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
28952913
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
28962914
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
28972915
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
28982916
mqd->cp_gfx_mqd_control = tmp;
28992917

29002918
/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2901-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
2919+
tmp = regCP_GFX_HQD_VMID_DEFAULT;
29022920
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
29032921
mqd->cp_gfx_hqd_vmid = 0;
29042922

29052923
/* set up default queue priority level
29062924
* 0x0 = low priority, 0x1 = high priority */
2907-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
2925+
tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
29082926
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
29092927
mqd->cp_gfx_hqd_queue_priority = tmp;
29102928

29112929
/* set up time quantum */
2912-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
2930+
tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
29132931
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
29142932
mqd->cp_gfx_hqd_quantum = tmp;
29152933

@@ -2931,7 +2949,7 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
29312949

29322950
/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
29332951
rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
2934-
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
2952+
tmp = regCP_GFX_HQD_CNTL_DEFAULT;
29352953
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
29362954
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
29372955
#ifdef __BIG_ENDIAN
@@ -2940,7 +2958,7 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
29402958
mqd->cp_gfx_hqd_cntl = tmp;
29412959

29422960
/* set up cp_doorbell_control */
2943-
tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
2961+
tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
29442962
if (prop->use_doorbell) {
29452963
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
29462964
DOORBELL_OFFSET, prop->doorbell_index);
@@ -2952,7 +2970,7 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
29522970
mqd->cp_rb_doorbell_control = tmp;
29532971

29542972
/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2955-
mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
2973+
mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;
29562974

29572975
/* active the queue */
29582976
mqd->cp_gfx_hqd_active = 1;
@@ -3047,14 +3065,14 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
30473065
mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
30483066

30493067
/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3050-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
3068+
tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
30513069
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
30523070
(order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));
30533071

30543072
mqd->cp_hqd_eop_control = tmp;
30553073

30563074
/* enable doorbell? */
3057-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3075+
tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
30583076

30593077
if (prop->use_doorbell) {
30603078
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
@@ -3083,7 +3101,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
30833101
mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
30843102

30853103
/* set MQD vmid to 0 */
3086-
tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
3104+
tmp = regCP_MQD_CONTROL_DEFAULT;
30873105
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
30883106
mqd->cp_mqd_control = tmp;
30893107

@@ -3093,7 +3111,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
30933111
mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
30943112

30953113
/* set up the HQD, this is similar to CP_RB0_CNTL */
3096-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
3114+
tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
30973115
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
30983116
(order_base_2(prop->queue_size / 4) - 1));
30993117
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
@@ -3118,7 +3136,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
31183136
tmp = 0;
31193137
/* enable the doorbell if requested */
31203138
if (prop->use_doorbell) {
3121-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3139+
tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
31223140
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
31233141
DOORBELL_OFFSET, prop->doorbell_index);
31243142

@@ -3133,17 +3151,17 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
31333151
mqd->cp_hqd_pq_doorbell_control = tmp;
31343152

31353153
/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3136-
mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
3154+
mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
31373155

31383156
/* set the vmid for the queue */
31393157
mqd->cp_hqd_vmid = 0;
31403158

3141-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
3159+
tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
31423160
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
31433161
mqd->cp_hqd_persistent_state = tmp;
31443162

31453163
/* set MIN_IB_AVAIL_SIZE */
3146-
tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
3164+
tmp = regCP_HQD_IB_CONTROL_DEFAULT;
31473165
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
31483166
mqd->cp_hqd_ib_control = tmp;
31493167

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