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AngeloGioacchino Del Regnoandersson
AngeloGioacchino Del Regno
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andersson
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arm64: dts: qcom: msm8998: Add DPU1 nodes
Add the required nodes to support the display hardware on msm8998. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> [konrad: update the commit msg and AGdR's email, rebase] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230805-topic-8998_dpu-v1-1-9d402dc1ecc0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Lines changed: 279 additions & 4 deletions

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‎arch/arm64/boot/dts/qcom/msm8998.dtsi‎

Lines changed: 279 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -316,6 +316,25 @@
316316
};
317317
};
318318

319+
dsi_opp_table: opp-table-dsi {
320+
compatible = "operating-points-v2";
321+
322+
opp-131250000 {
323+
opp-hz = /bits/ 64 <131250000>;
324+
required-opps = <&rpmpd_opp_low_svs>;
325+
};
326+
327+
opp-210000000 {
328+
opp-hz = /bits/ 64 <210000000>;
329+
required-opps = <&rpmpd_opp_svs>;
330+
};
331+
332+
opp-312500000 {
333+
opp-hz = /bits/ 64 <312500000>;
334+
required-opps = <&rpmpd_opp_nom>;
335+
};
336+
};
337+
319338
psci {
320339
compatible = "arm,psci-1.0";
321340
method = "smc";
@@ -2728,16 +2747,272 @@
27282747
"gpll0_div";
27292748
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
27302749
<&gcc GCC_MMSS_GPLL0_CLK>,
2731-
<0>,
2732-
<0>,
2733-
<0>,
2734-
<0>,
2750+
<&mdss_dsi0_phy 1>,
2751+
<&mdss_dsi0_phy 0>,
2752+
<&mdss_dsi1_phy 1>,
2753+
<&mdss_dsi1_phy 0>,
27352754
<0>,
27362755
<0>,
27372756
<0>,
27382757
<&gcc GCC_MMSS_GPLL0_DIV_CLK>;
27392758
};
27402759

2760+
mdss: display-subsystem@c900000 {
2761+
compatible = "qcom,msm8998-mdss";
2762+
reg = <0x0c900000 0x1000>;
2763+
reg-names = "mdss";
2764+
2765+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2766+
interrupt-controller;
2767+
#interrupt-cells = <1>;
2768+
2769+
clocks = <&mmcc MDSS_AHB_CLK>,
2770+
<&mmcc MDSS_AXI_CLK>,
2771+
<&mmcc MDSS_MDP_CLK>;
2772+
clock-names = "iface",
2773+
"bus",
2774+
"core";
2775+
2776+
power-domains = <&mmcc MDSS_GDSC>;
2777+
iommus = <&mmss_smmu 0>;
2778+
2779+
#address-cells = <1>;
2780+
#size-cells = <1>;
2781+
ranges;
2782+
2783+
status = "disabled";
2784+
2785+
mdss_mdp: display-controller@c901000 {
2786+
compatible = "qcom,msm8998-dpu";
2787+
reg = <0x0c901000 0x8f000>,
2788+
<0x0c9a8e00 0xf0>,
2789+
<0x0c9b0000 0x2008>,
2790+
<0x0c9b8000 0x1040>;
2791+
reg-names = "mdp",
2792+
"regdma",
2793+
"vbif",
2794+
"vbif_nrt";
2795+
2796+
interrupt-parent = <&mdss>;
2797+
interrupts = <0>;
2798+
2799+
clocks = <&mmcc MDSS_AHB_CLK>,
2800+
<&mmcc MDSS_AXI_CLK>,
2801+
<&mmcc MNOC_AHB_CLK>,
2802+
<&mmcc MDSS_MDP_CLK>,
2803+
<&mmcc MDSS_VSYNC_CLK>;
2804+
clock-names = "iface",
2805+
"bus",
2806+
"mnoc",
2807+
"core",
2808+
"vsync";
2809+
2810+
assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2811+
assigned-clock-rates = <19200000>;
2812+
2813+
operating-points-v2 = <&mdp_opp_table>;
2814+
power-domains = <&rpmpd MSM8998_VDDMX>;
2815+
2816+
mdp_opp_table: opp-table {
2817+
compatible = "operating-points-v2";
2818+
2819+
opp-171430000 {
2820+
opp-hz = /bits/ 64 <171430000>;
2821+
required-opps = <&rpmpd_opp_low_svs>;
2822+
};
2823+
2824+
opp-275000000 {
2825+
opp-hz = /bits/ 64 <275000000>;
2826+
required-opps = <&rpmpd_opp_svs>;
2827+
};
2828+
2829+
opp-330000000 {
2830+
opp-hz = /bits/ 64 <330000000>;
2831+
required-opps = <&rpmpd_opp_nom>;
2832+
};
2833+
2834+
opp-412500000 {
2835+
opp-hz = /bits/ 64 <412500000>;
2836+
required-opps = <&rpmpd_opp_turbo>;
2837+
};
2838+
};
2839+
2840+
ports {
2841+
#address-cells = <1>;
2842+
#size-cells = <0>;
2843+
2844+
port@0 {
2845+
reg = <0>;
2846+
2847+
dpu_intf1_out: endpoint {
2848+
remote-endpoint = <&mdss_dsi0_in>;
2849+
};
2850+
};
2851+
2852+
port@1 {
2853+
reg = <1>;
2854+
2855+
dpu_intf2_out: endpoint {
2856+
remote-endpoint = <&mdss_dsi1_in>;
2857+
};
2858+
};
2859+
};
2860+
};
2861+
2862+
mdss_dsi0: dsi@c994000 {
2863+
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2864+
reg = <0x0c994000 0x400>;
2865+
reg-names = "dsi_ctrl";
2866+
2867+
interrupt-parent = <&mdss>;
2868+
interrupts = <4>;
2869+
2870+
clocks = <&mmcc MDSS_BYTE0_CLK>,
2871+
<&mmcc MDSS_BYTE0_INTF_CLK>,
2872+
<&mmcc MDSS_PCLK0_CLK>,
2873+
<&mmcc MDSS_ESC0_CLK>,
2874+
<&mmcc MDSS_AHB_CLK>,
2875+
<&mmcc MDSS_AXI_CLK>;
2876+
clock-names = "byte",
2877+
"byte_intf",
2878+
"pixel",
2879+
"core",
2880+
"iface",
2881+
"bus";
2882+
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2883+
<&mmcc PCLK0_CLK_SRC>;
2884+
assigned-clock-parents = <&mdss_dsi0_phy 0>,
2885+
<&mdss_dsi0_phy 1>;
2886+
2887+
operating-points-v2 = <&dsi_opp_table>;
2888+
power-domains = <&rpmpd MSM8998_VDDCX>;
2889+
2890+
phys = <&mdss_dsi0_phy>;
2891+
phy-names = "dsi";
2892+
2893+
#address-cells = <1>;
2894+
#size-cells = <0>;
2895+
2896+
status = "disabled";
2897+
2898+
ports {
2899+
#address-cells = <1>;
2900+
#size-cells = <0>;
2901+
2902+
port@0 {
2903+
reg = <0>;
2904+
2905+
mdss_dsi0_in: endpoint {
2906+
remote-endpoint = <&dpu_intf1_out>;
2907+
};
2908+
};
2909+
2910+
port@1 {
2911+
reg = <1>;
2912+
2913+
mdss_dsi0_out: endpoint {
2914+
};
2915+
};
2916+
};
2917+
};
2918+
2919+
mdss_dsi0_phy: phy@c994400 {
2920+
compatible = "qcom,dsi-phy-10nm-8998";
2921+
reg = <0x0c994400 0x200>,
2922+
<0x0c994600 0x280>,
2923+
<0x0c994a00 0x1e0>;
2924+
reg-names = "dsi_phy",
2925+
"dsi_phy_lane",
2926+
"dsi_pll";
2927+
2928+
clocks = <&mmcc MDSS_AHB_CLK>,
2929+
<&rpmcc RPM_SMD_XO_CLK_SRC>;
2930+
clock-names = "iface", "ref";
2931+
2932+
#clock-cells = <1>;
2933+
#phy-cells = <0>;
2934+
2935+
status = "disabled";
2936+
};
2937+
2938+
mdss_dsi1: dsi@c996000 {
2939+
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2940+
reg = <0x0c996000 0x400>;
2941+
reg-names = "dsi_ctrl";
2942+
2943+
interrupt-parent = <&mdss>;
2944+
interrupts = <5>;
2945+
2946+
clocks = <&mmcc MDSS_BYTE1_CLK>,
2947+
<&mmcc MDSS_BYTE1_INTF_CLK>,
2948+
<&mmcc MDSS_PCLK1_CLK>,
2949+
<&mmcc MDSS_ESC1_CLK>,
2950+
<&mmcc MDSS_AHB_CLK>,
2951+
<&mmcc MDSS_AXI_CLK>;
2952+
clock-names = "byte",
2953+
"byte_intf",
2954+
"pixel",
2955+
"core",
2956+
"iface",
2957+
"bus";
2958+
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2959+
<&mmcc PCLK1_CLK_SRC>;
2960+
assigned-clock-parents = <&mdss_dsi1_phy 0>,
2961+
<&mdss_dsi1_phy 1>;
2962+
2963+
operating-points-v2 = <&dsi_opp_table>;
2964+
power-domains = <&rpmpd MSM8998_VDDCX>;
2965+
2966+
phys = <&mdss_dsi1_phy>;
2967+
phy-names = "dsi";
2968+
2969+
#address-cells = <1>;
2970+
#size-cells = <0>;
2971+
2972+
status = "disabled";
2973+
2974+
ports {
2975+
#address-cells = <1>;
2976+
#size-cells = <0>;
2977+
2978+
port@0 {
2979+
reg = <0>;
2980+
2981+
mdss_dsi1_in: endpoint {
2982+
remote-endpoint = <&dpu_intf2_out>;
2983+
};
2984+
};
2985+
2986+
port@1 {
2987+
reg = <1>;
2988+
2989+
mdss_dsi1_out: endpoint {
2990+
};
2991+
};
2992+
};
2993+
};
2994+
2995+
mdss_dsi1_phy: phy@c996400 {
2996+
compatible = "qcom,dsi-phy-10nm-8998";
2997+
reg = <0x0c996400 0x200>,
2998+
<0x0c996600 0x280>,
2999+
<0x0c996a00 0x10e>;
3000+
reg-names = "dsi_phy",
3001+
"dsi_phy_lane",
3002+
"dsi_pll";
3003+
3004+
clocks = <&mmcc MDSS_AHB_CLK>,
3005+
<&rpmcc RPM_SMD_XO_CLK_SRC>;
3006+
clock-names = "iface",
3007+
"ref";
3008+
3009+
#clock-cells = <1>;
3010+
#phy-cells = <0>;
3011+
3012+
status = "disabled";
3013+
};
3014+
};
3015+
27413016
mmss_smmu: iommu@cd00000 {
27423017
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
27433018
reg = <0x0cd00000 0x40000>;

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