[v2025.1]Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/ref_files/step3_validate

[wqyoung]

Hello,
I ran step1 and step2 successfully, but when execute "make aie_adder_hw" in step3_validate, I ran into the following error:

===>The following messages were generated while Compiling (bitstream) accelerator binary: adder Log file: /home/my/worktree/Viti-Tutorials-2025.1/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/ref_files/step3_validate/aie_work/_x/link/vivado/vpl/prj/prj.runs/impl_1/runme.log :
ERROR: [VPL 101-2] design did not meet timing - Design failed to meet timing.
Failed timing checks (paths):
{versal_dfx_platform_i/IsoReset/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C --> versal_dfx_platform_i/VitisRegion/clk_wizard_0/inst/clock_primitive_inst/MBUFGCE_CE_1_DLY_inst/clr_rise_det_reg/PRE}

Please check the routed checkpoint (dr_routed_timing.dcp) and timing summary report (dr_timing_summary.rpt) for more information.

ERROR: [VPL 101-3] sourcing script /home/my/worktree/Viti-Tutorials-2025.1/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/ref_files/step3_validate/aie_work/_x/link/vivado/vpl/scripts/impl_1/_full_write_device_image_pre.tcl failed

Could you please provide some suggestions on how to fix it?

Best Regards